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| mb91520 series 32 - bit microcontroller fr family fr81s mb91f522b/d/f/j/k/l,mb91f 523b/d/f/j/k/l, mb91f524b/d/f/j/k/l,mb91f525b/d/f/j/k/l,mb91f526b/d/f/j/k/l* data sheet (full production) publication number mb91f526l_ds705 - 00011 revision 2 . 0 issue date january 31, 2014 confidential
d a t a s h e e t mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential mb91520 series 32 - bit microcontroller fr family fr81s mb91f522b/d/f/j/k/l ,mb91f523b/d/f/j/k/l, mb91f524b/d/f/j/k/l,mb91f525b/d/f/j/k/l,mb91f526b/d/f/j/k/l* data sheet (full production) publication number mb91f526l_ds705 - 00011 revision 2 . 0 issue date january 31, 2014 confidential this document states the current technical specifications regar ding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. ? description the mb91520 series is a spansion 32 - bit microcontroller designed for automotive devices. this series contains the fr81s cpu which is compatible with the fr family. note : fr is a line of products of spansion inc . *:this series is a compositio n of the kind that adds hb/jb/kb/lb/sb/ub/wb/yb to the end of the above - mentioned each name of articles of presence, according to presence of sub - clock, csv initial value and lvd initial value. please see " ordering information" for details. spansion provides informa tion facilitating product development via the following website. the website contains information useful for customers. http://www.spansion.com/support/microcontrollers/pages/default.aspx d a t a s h e e t 2 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? features ? fr81s cpu core 32 - bit risc, load/store architecture, pipeline 5 - stage structure maximum operating frequency: 80 mhz (source oscillation = 4.0 mhz and 20 multiplied ( pll clock multiplication system ) ) general - purpose register : 32 bits 16 sets 16 - bit fixed length instructions ( basic instruction ) , 1 instruction per cycle instructions appropriate to embedded applications memory - to - memory transfer instru c tion bit processing instruction barrel shift order etc. high - level language support instructions function entry/exit instructions r egister content multi - load and store instructions bit search instructions logical 1 detection, 0 detection, and change - point detection branch instructions with delay slot overhead reduction during b r anch proces s register i nterlock function easy assembler writing the support at the built - in / instruction level of the multiplier signed 32 - bit multiplication: 5 cycles signed 16 - bit multiplication: 3 cycles interrupt ( pc/ps saving ) 6 cycles ( 16 priority levels) the harvard ar chitecture allows simultaneous execution of program and data access. instruction compatibility with the fr family built - in memory protection function ( mpu ) eight protection areas can b e specified commonly for instructions and the data. control access privi lege in both privilege mode and user mode. built - in fpu (f loating point arithmetic ) ieee754 compliant f loating - point register 32 - bit 16 sets ? peripheral functions clock generation (equipped with sscg function) main oscillation ( 4mhz to 16mhz ) sub oscilla t i on (32 khz to 100khz) or none sub oscillat i on pll multiplication rate : 1 to 20 times built - in program flash memory capacity mb91f522:256+64kb mb91f523:384+64kb mb91f524:512+64kb mb91f525:768+64kb mb91f526:1024+64kb flash memory for built - in data (wo rkflash) 64kb built - in ram capacity main ram mb91f522:48kb mb91f523:48kb mb91f524:64kb mb91f525:96kb mb91f526:128kb backup ram 8kb d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 3 confidential general - purpose ports: mb91f52xb 44 sets ( no sub oscillation ), 42 sets (sub oscillation) mb91f52xd 56 sets ( no sub oscill ation ), 54 sets (sub oscillation) mb91f52xf 76 sets ( no sub oscillation ), 74 sets (sub oscillation) mb91f52xj 96 sets ( no sub oscillation ), 94 sets (sub oscillation) mb91f52xk 120 sets ( no sub oscillation ), 11 8 sets (sub oscillation) mb91f52xl 152 sets ( no sub oscillation ), 150 sets (sub oscillation) included i 2 c open drain corresponding ports :16 sets external bus interface 2 2 - bit address, 16 - bit data dma controller up to 16 channels can be started simultaneously. 2 transfer factors ( internal peripher al request and software ) a/d converter ( successive approximation type) 12 - bit resolution : max. 48ch (32ch+16ch) conversion time : 1 s d/a converter (r - 2r type) 8 - bit resolution : 2 ch external interrupt input: 8 channels 2 unit s total 16 channels level ( "h" / "l"), or edge detection ( rising or falling ) enabled multi - function serial communication (built - in transmission/reception fifo memory ) : max.12 channels 5v to l erant input: 4 channels ch.6, ch.8, ch.9, ch.11 cmos hysteresis input < uart (asynchronous serial interface) > full - duplex double buffering system, 64 - step transmission fifo memory, 64 - step reception fifo memory parity or no parity is selectable . built - in dedicated baud rate generator an external clock can be used as the transfer clock parity, frame, and overrun error detection functions provided dma transfer support d a t a s h e e t 4 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential can controller (can) : 3 channels transfer speed : up to 1mbps 128 - transmission/reception message buffering : 1 channel (ch . 0) , 64 - transmission/reception message buffering : 2 chan nels (ch.1 and ch.2) ppg: 16 - bit max. 48 channels led drive output 4 channels 11ch to 14ch reload timer : 16 - bit max.8 channels free - run timer : 16 - bit 3 channels 32 - bit max 3 channels input capture : 16 - bit 4 channels (linked to the free - run timer) 32 - bit max 6 channels (linked to the free - run timer) output compare : 16 - bit 6 channels (linked to the free - run timer) 32 - bit max 6 channels (linked to the free - run timer) waveform generator : 6 channels up/ d own counter 8/16 - bit up/ d own co unter 2 channels real - time clock (rtc) (for day, hours, minutes, seconds) main or sub oscillation frequency can be selected for the operation clock calibration: r eal - time clock (rtc) of the subclock drive the main clock to sub clock ratio can be correct ed by setting the real - time clock prescaler clock supervisor monitoring abnormality ( by damage d quartz, etc.) of suboscillation (32 khz ) ( dual clock product s) of the outside and main oscillation (4 mhz ) when abnormality is detected, it switches to the cr clock. initial value on/off can be selected by the part number. base timer : max. 2 channels 16 - bit timer any of four pwm/ppg/pwc/reload timer functions can be selected and used a 32 - bit timer can be used in 2 channels of cascade mode crc generation watchd og timer hardware watchdog software watchdog ( possible to set the valid range for counter clearing ) nmi (non - maskable interrupt) interrupt controller interrupt request batch read the interrupt existence from two or more peripherals can be read by a series of register. i/o relocation peripheral function pins can be reassigned. low - power consumption mode sleep / stop / watch / sub run mode stop (power shutdown ) / watch (power shutdown) mode power - on rese t low - voltage detection reset ( independently monitor t he external power supply and the internal power supply ) the external power supply can select initial value on/off by the part number. device package : lqfp - 176/144/120/100/80/64 cmos 90nm technology power supplies 5v power supply the internal 1.2v is gene rated from 5v with the voltage step - down circuit. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 5 confidential ? product lineup ? product lineup comparison 64pin s mb91f522b mb91f523b mb91f524b mb91f525b mb91f526b system clock on chip pll clock multiple method minimum instruction execution time 12.5ns ( 80mhz ) flash capacity ( program) ( 256+64 ) kb ( 384+64 ) kb ( 512+64 ) k b ( 768+64 ) kb ( 1024+64 ) kb flash capacity ( data) 64kb ram capacity ( 48+8 ) kb ( 64+8 ) kb ( 96+8 ) kb ( 128+8 ) kb external bus i/f (22 address /16data/4cs ) no ne dma transfer 16ch 16 - bit base timer none free - run timer 16bit 3ch 32bit 1ch input capture 16bit 4ch 3 2bit 5ch output compare 16bit 6ch 32bit 4ch 16 - bit reload timer 7ch ppg 16bit 21ch up / down counter 2ch clock supervisor yes external interrupt 8ch 2units a/d converter 12bit 13ch ( 1unit ) 12bit 13ch ( 1unit ) d/a converter ( 8bit ) 1ch multi - function serial interface 8ch can 64msg 2 ch/128msg 1ch hardware watchdog timer yes crc formation yes low - voltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory protection function ( mpu ) yes floating point arithmetic ( fpu ) yes real time clock ( rtc ) yes general - purpose port ( #gpios ) 44 ports sscg yes sub clock yes cr oscillator yes ocd ( on chip debug ) yes tpu ( timing protection unit ) yes key code register yes waveform generator 6ch nmi request function yes operati on guaranteed temperature ( t a ) - 40c to +125c power supply 2.7v to 5.5v package lqfp - 64 d a t a s h e e t 6 mb91f526l_ds705 - 00011 - 2 v 0 - e , january 31, 2014 confidential ? product lineup comparison 80p in s mb91f522d mb91f523d mb91f524d mb91f525d MB91F526D system clock on chip pll clock multiple method minimum instruction execution time 12.5ns ( 80mhz ) flash capacity ( program) ( 256+64 ) kb ( 384+64 ) kb ( 512+64 ) kb ( 768+64 ) kb ( 1024+64 ) kb flash capacity ( data) 64kb ram capacity ( 48+8 ) kb ( 64+8 ) kb ( 96+8 ) kb ( 128+8 ) kb external bus i/f (22 address /16data/4cs ) none dma transfer 16ch 16 - bit b ase timer 1ch free - run timer 16bit 3ch 32bit 2ch input capture 16bit 4ch 32bit 5ch output compare 16bit 6ch 32bit 4ch 16 - bit reload timer 7ch ppg 16bit 27ch up / down counter 2ch clock supervisor yes external interrupt 8ch 2units a/d converter 12bit 16ch ( 1unit ) 12bit 16ch ( 1unit ) d/a converter ( 8bit ) 1ch multi - function serial interface 9ch can 64msg 2 ch/128msg 1ch hardware watchdog timer yes crc formation yes low - voltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory protection function ( mpu ) yes floating point arithmetic ( fpu ) yes real time clock ( rtc ) yes general - purpose port ( #gpios ) 56 ports sscg yes sub clock yes cr oscillator yes nmi request function yes ocd ( on chip debug ) yes tpu ( timing p rotection unit ) yes key code register yes waveform generator 6ch operation guaranteed temperature ( t a ) - 40c to +125c power supply 2.7v to 5.5v package lqfp - 80 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 7 confidential ? product lineup comparison 100 p in s mb91f522f mb91f523f mb91f524f mb91f525f mb91f526f system clock on chip pll clock multiple method minimum instruction execution time 12.5ns ( 80mhz ) flash capacity ( program) ( 256+64 ) kb ( 384+64 ) kb ( 512+64 ) kb ( 768+64 ) kb ( 1024+64 ) kb flash capacity ( data) 64kb ram capacity ( 48+8 ) kb ( 64+8 ) kb ( 96+8 ) kb ( 128+8 ) kb external bus i/f ( 22address /16data/4cs ) none dma transfer 16ch 16 - bit base timer 1ch free - run timer 16bit 3ch 32bit 3ch input capture 16bit 4ch 32bit 6ch output compare 16bit 6ch 32bit 6ch 16 - bit reload timer 8ch ppg 16bit 34ch up / down counter 2ch clock supervisor yes external interrupt 8ch 2units a/d converter 12bit 21ch ( 1unit ) 12bit 16ch ( 1unit ) d/a converter ( 8bit ) 2ch multi - function serial interface 12ch can 64msg 2ch/128msg 1ch hardware watchdog timer yes crc formation yes low - vo ltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory protection function ( mpu ) yes floating point arithmetic ( fpu ) yes real time clock ( rtc ) yes general - purpose port ( #gpios ) 76 ports sscg yes sub clock yes cr o scillator yes nmi request function yes ocd ( on chip debug ) yes tpu ( timing protection unit ) yes key code register yes waveform generator 6ch operation guaranteed temperature ( t a ) - 40c to +125c power supply 2.7v to 5.5v package lqfp - 100 d a t a s h e e t 8 mb91f526l_ds705 - 00011 - 2 v 0 - e , january 31, 2014 confidential ? produc t lineup comparison 120pin s mb91f522j mb91f523j mb91f524j mb91f525j mb91f526j system clock on chip pll clock multiple method minimum instruction execution time 12.5ns ( 80mhz ) flash capacity ( program) ( 256+64 ) kb ( 384+64 ) kb ( 512+64 ) kb ( 768+64 ) kb ( 1024+6 4 ) kb flash capacity ( data) 64kb ram capacity ( 48+8 ) kb ( 64+8 ) kb ( 96+8 ) kb ( 128+8 ) kb external bus i/f ( 22address /16data/4cs ) none dma transfer 16ch 16 - bit base timer 2ch free - run timer 16bit 3ch 32bit 3ch input capture 16bit 4ch 32bit 6ch output comp are 16bit 6ch 32bit 6ch 16 - bit reload timer 8ch ppg 16bit 38ch up / down counter 2ch clock supervisor yes external interrupt 8ch 2units a/d converter 12bit 26ch ( 1unit ) 12bit 16ch ( 1unit ) d/a converter ( 8bit) 2ch multi - function serial interface 12ch can 64msg 2ch/128msg 1ch hardware watchdog timer yes crc formation yes low - voltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory protection function ( mpu ) yes floating point arithmetic ( fpu ) yes real time clock ( rtc ) yes general - purpose port ( #gpios ) 96 ports sscg yes sub clock yes cr oscillator yes nmi request function yes ocd ( on chip debug ) yes tpu ( timing protection unit ) yes key code register yes waveform generator 6ch operation guaranteed temper ature ( t a ) - 40c to +125c power supply 2.7v to 5.5v package lqfp - 120 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 9 confidential ? product lineup comparison 144pin s mb91f522k mb91f523k mb91f524k mb91f525k mb91f526k system clock on chip pll clock multiple method minimum instruction execution time 12.5ns ( 80m hz ) flash capacity ( program) ( 256+64 ) kb ( 384+64 ) kb ( 512+64 ) kb ( 768+64 ) kb ( 1024+64 ) kb flash capacity ( data) 64kb ram capacity ( 48+8 ) kb ( 64+8 ) kb ( 96+8 ) kb ( 128+8 ) kb external bus i/f ( 22address /16data/4cs ) yes dma transfer 16ch 16 - bit base timer 2ch fr ee - run timer 16bit 3ch 32bit 3ch input capture 16bit 4ch 32bit 6ch output compare 16bit 6ch 32bit 6ch 16 - bit reload timer 8ch ppg 16bit 44ch up / down counter 2ch clock supervisor yes external interrupt 8ch 2units a/d converter 12bit 32ch ( 1unit ) 12b it 16ch ( 1unit ) d/a converter ( 8bit) 2ch multi - function serial interface 12ch can 64msg 2ch/128msg 1ch hardware watchdog timer yes crc formation yes low - voltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory pro tection function ( mpu ) yes floating point arithmetic ( fpu ) yes real time clock ( rtc ) yes general - purpose port ( #gpios ) 120 ports sscg yes sub clock yes cr oscillator yes nmi request function yes ocd ( on chip debug ) yes tpu ( timing protection unit ) yes key code register yes waveform generator 6ch operation guaranteed temperature ( t a ) - 40c to +125c power supply 2.7v to 5.5v package lqfp - 144 d a t a s h e e t 10 mb91f526l_ds705 - 00011 - 2 v 0 - e , january 31, 2014 confidential ? product lineup comparison 176pin s mb91f522l mb91f523l mb91f524l mb91f525l mb91f526l system clock on chip pll clock multiple method minimum instruction execution time 12.5ns ( 80mhz ) flash capacity ( program) ( 256+64 ) kb ( 384+64 ) kb ( 512+64 ) kb ( 768+64 ) kb ( 1024+64 ) kb flash capacity ( data) 64kb ram capacity ( 48+8 ) kb ( 64+8 ) kb ( 96+8 ) kb ( 128+8 ) kb external bus i/f ( 22address /16data/4cs ) yes dma transfer 16ch 16 - bit base timer 2ch free - run timer 16bit 3ch 32bit 3ch input capture 16bit 4ch 32bit 6ch output compare 16bit 6ch 32bit 6ch 16 - bit reload timer 8ch ppg 16bit 48ch up / down counter 2ch clock sup ervisor yes external interrupt 8ch 2units a/d converter 12bit 32ch ( 1unit ) 12bit 16ch ( 1unit ) d/a converter ( 8bit ) 2ch multi - function serial interface 12ch can 64msg 2ch/128msg 1ch hardware watchdog timer yes crc formation yes low - voltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory protection function ( mpu ) yes floating point arithmetic ( fpu ) yes real time clock ( rtc ) yes general - purpose port ( #gpios ) 152 ports sscg yes sub clock yes cr oscillator yes nmi request function yes ocd ( on chip debug ) yes tpu ( timing protection unit ) yes key code register yes waveform generator 6ch operation guaranteed temperature ( t a ) - 40c to +125c power supply 2.7v to 5.5v package lqfp - 176 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 11 confidential ? table for clock super visor and external low voltage detection reset initial value on/off clock csv initial value lvd initial value function single on on s off u off on h off k dual on on w off y off on j off l ? ? see the table for clock supervisor and external low voltage detection reset initial value on/off. d a t a s h e e t 12 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? pin assignment ? mb91f52xb mb91f522b , mb91f523b , mb91f524b , mb91f525b, mb91f526b (top view) vcc p011/wot/sot2_1/tioa0_0/int3_1 p006/scs2_0/adtg1_1/int2_1/tx2(64) p005/sck2_0/adtg0_1/int7_1/rx2(64) c vss rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p126/sin0_0/int6_0 debugif 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vss 1 48 p122/sin6_0/an31/ocu8_0/int9_1 p020/sin3_1/trg3_0/tin0_2/rto5_1 2 47 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p024/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 3 46 p115/rx1_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p027/scs40_1/ppg27_0/tot0_0/rto3_1 4 45 p110/tx1(64)/scs63_0/an22 p032/scs43_1/ppg30_0/tot3_0/rto2_1 5 44 nm ix p033/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 6 43 p105/scs71_0/an17/ppg13_0 p034/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 7 42 p104/scs72_0/an16/ppg12_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 8 41 p103/scs73_0/an15/ppg11_0 p035/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 9 40 p102/sin7_0/an14/ppg10_0/int10_0 p036/scs8_0/ocu7_1/tot5_0/bin0_0 10 39 avcc0 p040/ppg23_1/tot7_0/ain1_0/sin0_1 11 38 avrh0 p041/sin9_0/icu9_1/bin1_0/int12_0 12 37 avs s 0/avrl0 p042/sot9_0/an47/icu8_1/trg0_1/zin1_0 13 36 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p045/sck9_0/an46/icu5_1/trg3_1/tot1_2 14 35 p096/rx0(128)/sot11_0/sda11/an10/int0_0 p047/an45/trg8_0/tin3_2/sot0_1 15 34 p093/tx0_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 p053/an44/ppg35_0/int14_1/sck0_1 16 33 vss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p055/sin10_0/an43/ppg37_0/tin4_1 avcc1 p057/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p087/dao0/ppg7_0/int8_0 vcc top view mb91f522b, mb91f523b, mb91f524b, mb91f525b, mb91f526b lqfp-64 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 13 confidential ? mb91f52xd mb91f522d , mb91f523d , mb91f524d , mb91f525d, MB91F526D (top view) vcc p011/wot/sot2_1/tioa0_0/int3_1 p006/scs2_0/adtg1_1/int2_1/tx2(64) p005/sck2_0/adtg0_1/int7_1/rx2(64) p003/sin2_0/tiob1_1/int3_0 p001/sot1_0/tioa1_1 c vss rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p127/sot0_0 p126/sin0_0/int6_0 debugif vcc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vss 1 60 vss p020/sin3_1/trg3_0/tin0_2/rto5_1 2 59 p122/sin6_0/an31/ocu8_0/int9_1 p024/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 3 58 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p026/sck4_1/ppg26_0/tin3_0 4 57 p115/rx1_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p027/scs40_1/ppg27_0/tot0_0/rto3_1 5 56 p114/scs61_0/an26/ppg18_0/rto2_0 p031/scs42_1/ppg29_0/tot2_0 6 55 p110/tx1(64)/scs63_0/an22 p032/scs43_1/ppg30_0/tot3_0/rto2_1 7 54 nm ix p033/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 8 53 p107/an19/ppg15_0 p034/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 9 52 p105/scs71_0/an17/ppg13_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 10 51 p104/scs72_0/an16/ppg12_0 p035/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 11 50 p103/scs73_0/an15/ppg11_0 p036/scs8_0/ocu7_1/tot5_0/bin0_0 12 49 p102/sin7_0/an14/ppg10_0/int10_0 p040/ppg23_1/tot7_0/ain1_0/sin0_1 13 48 p100/sck7_0/scl7/an12/ppg8_0 p041/sin9_0/icu9_1/bin1_0/int12_0 14 47 avcc0 p042/sot9_0/an47/icu8_1/trg0_1/zin1_0 15 46 avrh0 p044/scs9_0/icu6_1/trg2_1 16 45 avs s 0/avrl0 p045/sck9_0/an46/icu5_1/trg3_1/tot1_2 17 44 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p047/an45/trg8_0/tin3_2/sot0_1 18 43 p096/rx0(128)/sot11_0/sda11/an10/int0_0 p053/an44/ppg35_0/int14_1/sck0_1 19 42 p093/tx0_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 vcc 20 41 vss 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vss p055/sin10_0/an43/ppg37_0/tin4_1 avcc1 p057/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p153/sck5_0/scl5/an32/frck1_1/int4_1 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p087/dao0/ppg7_0/int8_0 vcc top view mb91f522d, mb91f523d, mb91f524d, mb91f525d, MB91F526D lqfp-80 d a t a s h e e t 14 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? mb91f52xf mb91f522f , mb91f523f , mb91f524f , mb91f525f , mb91f526f (top view) vcc p011/wot/sot2_1/tioa0_0/int3_1 p006/scs2_0/adtg1_1/int2_1 p005/sck2_0/adtg0_1/int7_1 p003/sin2_0/tiob1_1/int3_0 p001/sot1_0/tioa1_1 p000/sin1_0/tioa0_1/int2_0 c vss p144/sck1_1 p134/rx2(64)/scs1_1/icu7_0/int7_0 p133/tx2(64) rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p130/sck0_0 p127/sot0_0 p126/sin0_0/int6_0 debugif vcc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vss 1 75 vss p020/sin3_1/trg3_0/tin0_2/rto5_1 2 74 p122/sin6_0/an31/ocu8_0/int9_1 p024/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 3 73 p117/scs60_0/an29/ppg21_0/rto5_0 p025/sot4_1/ppg25_0/tin2_0 4 72 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p026/sck4_1/ppg26_0/tin3_0 5 71 p115/rx1_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p027/scs40_1/ppg27_0/tot0_0/rto3_1 6 70 p114/scs61_0/an26/ppg18_0/rto2_0 p030/scs41_1/ppg28_0/tot1_0 7 69 p111/rx1(64)/scs62_0/an23/int1_0 p031/scs42_1/ppg29_0/tot2_0 8 68 p110/tx1(64)/scs63_0/an22 p032/scs43_1/ppg30_0/tot3_0/rto2_1 9 67 nmix p033/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 10 66 p107/an19/ppg15_0 p034/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 11 65 p106/scs70_0/an18/ppg14_0 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0 12 64 p105/scs71_0/an17/ppg13_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 13 63 p104/scs72_0/an16/ppg12_0 p035/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 14 62 p103/scs73_0/an15/ppg11_0 p036/scs8_0/ocu7_1/tot5_0/bin0_0 15 61 p102/sin7_0/an14/ppg10_0/int10_0 p037/ocu6_1/tot6_0/zin0_0 16 60 p101/sot7_0/sda7/an13/ppg9_0 p040/ppg23_1/tot7_0/ain1_0/sin0_1 17 59 p100/sck7_0/scl7/an12/ppg8_0 p041/sin9_0/icu9_1/bin1_0/int12_0 18 58 avcc0 p042/sot9_0/an47/icu8_1/trg0_1/zin1_0 19 57 avrh0 p043/icu7_1/trg1_1 20 56 avss0/avrl0 p044/scs9_0/icu6_1/trg2_1 21 55 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p045/sck9_0/an46/icu5_1/trg3_1/tot1_2 22 54 p096/rx0(128)/sot11_0/sda11/an10/int0_0 p047/an45/trg8_0/tin3_2/sot0_1 23 53 p095/tx0(128)/scs11_0/an9 p053/an44/ppg35_0/int14_1/sck0_1 24 52 p093/tx0_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 vcc 25 51 vss 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vss p055/sin10_0/an43/ppg37_0/tin4_1 avcc1 p057/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view mb91f522f, mb91f523f, mb91f524f, mb91f525f, mb91f526f lqfp-100 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 15 confidential ? mb91f52xj mb91f522j , mb91f523j , mb91f524j , mb91f525j , mb91f526j (top view) vcc p011/wot/sot2_1/tioa0_0/int3_1 p010 p007 p006/scs2_0/adtg1_1/int2_1 p005/sck2_0/adtg0_1/int7_1 p003/sin2_0/tiob1_1/int3_0 p002/sck1_0/tiob0_1 p001/sot1_0/tioa1_1 p000/sin1_0/tioa0_1/int2_0 c vss p144/sck1_1 p134/rx2(64)/scs1_1/icu7_0/int7_0 p133/tx2(64) p132/scs1_0/adtg1_0 rstx x0a/p136 x1a/p135 / dtti_0 vss x1 x0 md1 md0 p130/sck0_0 p127/sot0_0 p126/sin0_0/int6_0 p125/ocu11_0 debugif vcc 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 vss 1 90 vss p020/sin3_1/trg3_0/tin0_2/rto5_1 2 89 p122/sin6_0/an31/ocu8_0/int9_1 p021/sot3_1/trg6_1/trg4_0 3 88 p120/an30/ocu6_0/ppg22_0/int9_0 p022/sck3_1/trg7_1/trg5_0 4 87 p117/scs60_0/an29/ppg21_0/rto5_0 p023/scs3_1/ppg32_0/tin0_0 5 86 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p024/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 6 85 p115/rx1_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p025/sot4_1/ppg25_0/tin2_0 7 84 p114/scs61_0/an26/ppg18_0/rto2_0 p026/sck4_1/ppg26_0/tin3_0 8 83 p113/an25/ppg17_0/rto1_0 p027/scs40_1/ppg27_0/tot0_0/rto3_1 9 82 p112/an24/ppg16_0/rto0_0 p030/scs41_1/ppg28_0/tot1_0 10 81 p111/rx1(64)/scs62_0/an23/int1_0 p031/scs42_1/ppg29_0/tot2_0 11 80 p110/tx1(64)/scs63_0/an22 p032/scs43_1/ppg30_0/tot3_0/rto2_1 12 79 nmix p033/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 13 78 p155/an21 p034/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 14 77 p154/an20 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0 15 76 p107/an19/ppg15_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 16 75 p106/scs70_0/an18/ppg14_0 p035/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 17 74 p105/scs71_0/an17/ppg13_0 p036/scs8_0/ocu7_1/tot5_0/bin0_0 18 73 p104/scs72_0/an16/ppg12_0 p037/ocu6_1/tot6_0/zin0_0 19 72 p103/scs73_0/an15/ppg11_0 p040/ppg23_1/tot7_0/ain1_0/sin0_1 20 71 p102/sin7_0/an14/ppg10_0/int10_0 p041/sin9_0/icu9_1/bin1_0/int12_0 21 70 p101/sot7_0/sda7/an13/ppg9_0 p042/sot9_0/an47/icu8_1/trg0_1/zin1_0 22 69 p100/sck7_0/scl7/an12/ppg8_0 p043/icu7_1/trg1_1 23 68 avcc0 p044/scs9_0/icu6_1/trg2_1 24 67 avrh0 p045/sck9_0/an46/icu5_1/trg3_1/tot1_2 25 66 avss0/avrl0 p046/icu4_1/trg4_1 26 65 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p047/an45/trg8_0/tin3_2/sot0_1 27 64 p096/rx0(128)/sot11_0/sda11/an10/int0_0 p050/trg5_1/ppg33_0 28 63 p095/tx0(128)/scs11_0/an9 p053/an44/ppg35_0/int14_1/sck0_1 29 62 p093/tx0_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 vcc 30 61 vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vss p055/sin10_0/an43/ppg37_0/tin4_1 p056/icu9_0/ppg0_1/icu0_1/tin5_1/dtti_2 avcc1 p057/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p074/sck4_0/scl4 p075/sin3_0/int4_0 p076/sot3_0/sda3 p077/sck3_0/scl3 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view mb91f522j, mb91f523j, mb91f524j, mb91f525j, mb91f526j lqfp-120 d a t a s h e e t 16 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? mb91f52xk mb91f522k , mb91f523k , mb91f524k , mb91f525k , mb91f526k (top view) vcc p014/d28/tiob1_0 p013/d27/tioa1_0 p012/d26/tiob0_0 p011/wot/d25/sot2_1/tioa0_0/int3_1 p010/d24 p007/d23 p006/d22/scs2_0/adtg1_1/int2_1 p005/d21/sck2_0/adtg0_1/int7_1 p004/d20/sot2_0 p003/d19/sin2_0/tiob1_1/int3_0 p002/d18/sck1_0/tiob0_1 p001/d17/sot1_0/tioa1_1 p000/d16/sin1_0/tioa0_1/int2_0 c vss p144/sck1_1 p134/rx2(64)/scs1_1/icu7_0/int7_0 p133/tx2(64) p132/scs1_0/adtg1_0 p131/adtg0_0 rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p130/sck0_0 p127/sot0_0 p126/sin0_0/int6_0 p125/ocu11_0 p124/ocu10_0 debugif vcc 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vss 1 108 vss p015/d29/trg0_0 2 107 p123/ocu9_0 p016/d30/trg1_0 3 106 p122/sin6_0/an31/ocu8_0/int9_1 p017/d31/trg2_0 4 105 p121/ocu7_0/ppg23_0 p020/asx/sin3_1/trg3_0/tin0_2/rto5_1 5 104 p120/an30/ocu6_0/ppg22_0/int9_0 p021/cs0x/sot3_1/trg6_1/trg4_0 6 103 p117/scs60_0/an29/ppg21_0/rto5_0 p022/cs1x/sck3_1/trg7_1/trg5_0 7 102 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p023/rdx/scs3_1/ppg32_0/tin0_0 8 101 p115/rx1_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p024/wr0x/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 9 100 p114/scs61_0/an26/ppg18_0/rto2_0 p025/wr1x/sot4_1/ppg25_0/tin2_0 10 99 p113/an25/ppg17_0/rto1_0 p026/a00/sck4_1/ppg26_0/tin3_0 11 98 p112/an24/ppg16_0/rto0_0 p027/a01/scs40_1/ppg27_0/tot0_0/rto3_1 12 97 p111/rx1(64)/scs62_0/an23/int1_0 p030/a02/scs41_1/ppg28_0/tot1_0 13 96 p110/tx1(64)/scs63_0/an22 p031/a03/scs42_1/ppg29_0/tot2_0 14 95 nmix p032/a04/scs43_1/ppg30_0/tot3_0/rto2_1 15 94 p155/an21 p033/a05/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 16 93 p154/an20 p034/a06/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 17 92 p107/an19/ppg15_0 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0 18 91 p106/scs70_0/an18/ppg14_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 19 90 p105/scs71_0/an17/ppg13_0 p035/a07/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 20 89 p104/scs72_0/an16/ppg12_0 p036/a08/scs8_0/ocu7_1/tot5_0/bin0_0 21 88 p103/scs73_0/an15/ppg11_0 p037/a09/ocu6_1/tot6_0/zin0_0 22 87 p102/sin7_0/an14/ppg10_0/int10_0 p040/a10/ppg23_1/tot7_0/ain1_0/sin0_1 23 86 p101/sot7_0/sda7/an13/ppg9_0 p041/a11/sin9_0/icu9_1/bin1_0/int12_0 24 85 p100/sck7_0/scl7/an12/ppg8_0 p042/a12/sot9_0/an47/icu8_1/trg0_1/zin1_0 25 84 avcc0 p043/a13/icu7_1/trg1_1 26 83 avrh0 p044/a14/scs9_0/icu6_1/trg2_1 27 82 avss0/avrl0 p045/a15/sck9_0/an46/icu5_1/trg3_1/tot1_2 28 81 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p046/a16/icu4_1/trg4_1 29 80 p096/rx0(128)/sot11_0/sda11/an10/int0_0 p047/a17/an45/trg8_0/tin3_2/sot0_1 30 79 p095/tx0(128)/scs11_0/an9 p050/a18/trg5_1/ppg33_0 31 78 p094/an8/icu4_0/tot3_1 p051/a19/trg9_0 32 77 p093/tx0_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 p052/a20/ppg34_0/int14_0 33 76 p092/an6/ppg40_1/icu2_0/tot0_1 p053/a21/an44/ppg35_0/int14_1/sck0_1 34 75 p091/an5/ppg41_1/icu1_0/tin3_1 p054/sysclk/ppg36_0 35 74 p090/an4/icu0_0/tin2_1 vcc 36 73 vss 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vss p055/cs2x/sin10_0/an43/ppg37_0/tin4_1 p056/cs3x/icu9_0/ppg0_1/icu0_1/tin5_1/dtti_2 avcc1 p057/rdy/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 p142/sck10_0/scl10/ppg38_0/tin7_1 p143/sot10_0/sda10/ppg39_0/tot4_1 p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p074/sck4_0/scl4 p075/sin3_0/int4_0 p076/sot3_0/sda3 p077/sck3_0/scl3 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p080/scs52_0/ppg0_0 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p083/scs50_0/an2/ppg3_0 p084/scs51_0/an3/ppg4_0 p085/ppg5_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view mb91f522k, mb91f523k, mb91f524k, mb91f525k, mb91f526k lqfp-144 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 17 confidential ? mb91f52xl mb91f522l, mb91f523l , mb91f524l , mb91f525l , mb91f526l (top view) vcc p014/d28/tiob1_0 p013/d27/tioa1_0 p167/ppg35_1 p012/d26/tiob0_0 p011/wot/d25/sot2_1/tioa0_0/int3_1 p010/d24 p166/ppg34_1 p007/d23 p006/d22/scs2_0/adtg1_1/int2_1 p165/ppg33_1 p005/d21/sck2_0/adtg0_1/int7_1 p164/ppg32_1 p004/d20/sot2_0 p003/d19/sin2_0/tiob1_1/int3_0 p002/d18/sck1_0/tiob0_1 p001/d17/sot1_0/tioa1_1 p000/d16/sin1_0/tioa0_1/int2_0 c vss p144/sck1_1 p134/rx2(64)/scs1_1/icu7_0/int7_0 p133/tx2(64) p132/scs1_0/adtg1_0 p131/adtg0_0 rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p163/trg6_2 p162/trg5_2 p130/sck0_0 p127/sot0_0 p126/sin0_0/int6_0 p125/ocu11_0 p124/ocu10_0 p161/ppg31_1 p160/ppg30_1 debugif vcc 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 vss 1 132 vss p015/d29/trg0_0 2 131 p123/ocu9_0 p016/d30/trg1_0 3 130 p197/ppg29_1 p170/ppg36_1 4 129 p122/sin6_0/an31/ocu8_0/int9_1 p017/d31/trg2_0 5 128 p121/ocu7_0/ppg23_0 p171/ppg37_1 6 127 p120/an30/ocu6_0/ppg22_0/int9_0 p020/asx/sin3_1/trg3_0/tin0_2/rto5_1 7 126 p196/frck3_1/ppg28_1 p021/cs0x/sot3_1/trg6_1/trg4_0 8 125 p117/scs60_0/an29/ppg21_0/rto5_0 p022/cs1x/sck3_1/trg7_1/trg5_0 9 124 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p023/rdx/scs3_1/ppg32_0/tin0_0 10 123 p115/rx1_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p024/wr0x/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 11 122 p114/scs61_0/an26/ppg18_0/rto2_0 p025/wr1x/sot4_1/ppg25_0/tin2_0 12 121 p195/frck4_1/ppg27_1 p172/ppg38_1 13 120 p194/frck5_1/ppg26_1 p026/a00/sck4_1/ppg26_0/tin3_0 14 119 p113/an25/ppg17_0/rto1_0 p027/a01/scs40_1/ppg27_0/tot0_0/rto3_1 15 118 p112/an24/ppg16_0/rto0_0 p173/ppg39_1 16 117 p111/rx1(64)/scs62_0/an23/int1_0 p030/a02/scs41_1/ppg28_0/tot1_0 17 116 p110/tx1(64)/scs63_0/an22 p031/a03/scs42_1/ppg29_0/tot2_0 18 115 nmix p032/a04/scs43_1/ppg30_0/tot3_0/rto2_1 19 114 p155/an21 p033/a05/ppg31_0/icu3_3/tin4_0/rto1_1 /sck3_2 20 113 p154/an20 p034/a06/ocu11_1/icu2_3/tin5_0/rto0_1 /sot3_2 21 112 p193/ppg25_1 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0 22 111 p107/an19/ppg15_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 23 110 p106/scs70_0/an18/ppg14_0 p035/a07/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 24 109 p105/scs71_0/an17/ppg13_0 p036/a08/scs8_0/ocu7_1/tot5_0/bin0_0 25 108 p104/scs72_0/an16/ppg12_0 p037/a09/ocu6_1/tot6_0/zin0_0 26 107 p103/scs73_0/an15/ppg11_0 p174/trg8_1 27 106 p102/sin7_0/an14/ppg10_0/int10_0 p175/trg9_1 28 105 p101/sot7_0/sda7/an13/ppg9_0 p040/a10/ppg23_1/tot7_0/ain1_0/sin0_1 29 104 p100/sck7_0/scl7/an12/ppg8_0 p041/a11/sin9_0/icu9_1/bin1_0/int12_0 30 103 avcc0 p042/a12/sot9_0/an47/icu8_1/trg0_1/zin1_0 31 102 avrh0 p043/a13/icu7_1/trg1_1 32 101 avss0/avrl0 p044/a14/scs9_0/icu6_1/trg2_1 33 100 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p045/a15/sck9_0/an46/icu5_1/trg3_1/tot1_2 34 99 p096/rx0(128)/sot11_0/sda11/an10/int0_0 p046/a16/icu4_1/trg4_1 35 98 p095/tx0(128)/scs11_0/an9 p176/trg10_0 36 97 p094/an8/icu4_0/tot3_1 p047/a17/an45/trg8_0/tin3_2/sot0_1 37 96 p093/tx0_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 p177/trg11_0 38 95 p192/ppg24_1/tot1_1 p050/a18/trg5_1/ppg33_0 39 94 p092/an6/ppg40_1/icu2_0/tot0_1 p051/a19/trg9_0 40 93 p091/an5/ppg41_1/icu1_0/tin3_1 p052/a20/ppg34_0/int14_0 41 92 p090/an4/icu0_0/tin2_1 p053/a21/an44/ppg35_0/int14_1/sck0_1 42 91 p191/tin1_1 p054/sysclk/ppg36_0 43 90 p190/tin0_1 vcc 44 89 vss 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 vss p055/cs2x/sin10_0/an43/ppg37_0/tin4_1 p180/ppg40_0 p181/ppg41_0 p056/cs3x/icu9_0/ppg0_1/icu0_1/tin5_1/dtti_2 avcc1 p057/rdy/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 p142/sck10_0/scl10/ppg38_0/tin7_1 p143/sot10_0/sda10/ppg39_0/tot4_1 p182/ppg42_0 p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p183/ppg43_0 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p184/ppg44_0 p185/ppg45_0 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p186/ppg46_0 p187/ppg47_0 p074/sck4_0/scl4 p075/sin3_0/int4_0 p076/sot3_0/sda3 p077/sck3_0/scl3 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p080/scs52_0/ppg0_0 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p083/scs50_0/an2/ppg3_0 p084/scs51_0/an3/ppg4_0 p085/ppg5_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view mb91f522l, mb91f523l, mb91f524l, mb91f525l, mb91f526l lqfp-176 d a t a s h e e t 18 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? pin description pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - - - 2 2 p015 - a general - purpose i/o port d29 - external bus data bit29 i/o (0) trg0_0 - ppg trigger 0 input (0) - - - - 3 3 p016 - a general - purpose i/o port d30 - external bus data bit30 i/o (0) trg1_0 - ppg trigger 1 input (0) - - - - - 4 p170 - a general - purpose i/o port ppg36_1 - ppg ch.36 output (1) - - - - 4 5 p017 - a general - purpose i/o port d31 - external bus data bit31 i/o (0) trg2_0 - ppg trigger 2 input (0) - - - - - 6 p171 - a general - purpose i/o port ppg37_1 - ppg ch.37 output (1) 2 2 2 2 5 7 p020 - f general - purpose i/o port asx - external bus/address strobe outpu t sin3_1 - multi - function serial ch.3 serial data input (1) trg3_0 - ppg trigger 3 input (0) tin0_2 - reload timer ch.0 event input (2) rto5_1 - waveform generator ch.5 output pin (1) - - - 3 6 8 p021 - a general - purpose i /o port cs0x - external bus chip select 0 output sot3_1 - multi - function serial ch.3 serial data output (1) trg6_1 - ppg trigger 6 input (1) trg4_0 - ppg trigger 4 input (0) - - - 4 7 9 p022 - f general - purpose i/o port cs1x - external bus chip select 1 output sck3_1 - multi - function serial ch.3 clock i/o (1) trg7_1 - ppg trigger 7 input (1) trg5_0 - ppg trigger 5 input (0) - - - 5 8 10 p023 - a general - purpose i/o port rdx - extern al bus/read strobe output scs3_1 - serial chip select 3 output (1) ppg32_0 - ppg ch.32 output (0) tin0_0 - reload timer ch.0 event input (0) 3 3 3 6 9 11 p024 - f general - purpose i/o port wr0x - external bus/write strobe 0 output sin4_1 - multi - function serial ch.4 serial data input (1) ppg24_0 - ppg ch.24 output (0) tin1_0 - reload timer ch.1 event input (0) rto4_1 - waveform generator ch.4 output pin (1) int15_0 - int15 external in terrupt input (0) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 19 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - 4 7 10 12 p025 - a general - purpose i/o port wr1x - external bus/write strobe 1 output sot4_1 - multi - function serial ch.4 serial data output (1) ppg25_0 - ppg ch.25 output (0) tin2_0 - reload timer ch.2 event input (0) - - - - - 13 p172 - a general - purpose i/o port ppg38_1 - ppg ch.38 output (1) - 4 5 8 11 14 p026 - f general - purpose i/o port a00 - external bus/ address bit 0 output (0) sck4_1 - multi - function ser ial ch.4 clock i/o (1) ppg26_0 - ppg ch.26 output (0) tin3_0 - reload timer ch.3 event input (0) 4 5 6 9 12 15 p027 - a general - purpose i/o port a01 - external bus/ address bit 1 output (0) scs40_1 - serial chip select 40 i/o (1) ppg27_0 - ppg ch.27 output (0) tot0_0 - reload timer ch.0 output (0) rto3_1 - waveform generator ch.3 output pin (1) - - - - - 16 p173 - a general - purpose i/o port ppg39_1 - ppg ch.39 output (1) - - 7 10 13 17 p030 - a general - purpose i/o port a02 - external bus/ address bit 2 output (0) scs41_1 - serial chip select 41 output (1) ppg28_0 - ppg ch.28 output (0) tot1_0 - reload timer ch.1 output (0) - 6 8 11 14 18 p031 - a general - purpose i /o port a03 - external bus/ address bit 3 output (0) scs42_1 - serial chip select 42 output (1) ppg29_0 - ppg ch.29 output (0) tot2_0 - reload timer ch.2 output (0) 5 7 9 12 15 19 p032 - a general - purpose i/o port a04 - external bus/ address bit 4 output (0) scs43_1 - serial chip select 43 output (1) ppg30_0 - ppg ch.30 output (0) tot3_0 - reload timer ch.3 output (0) rto2_1 - waveform generator ch.2 output pin (1) 6 8 10 13 16 20 p033 - a general - purpose i/o port a05 - external bus/ address bit 5 output (0) ppg31_0 - ppg ch.31 output (0) icu3_3 - input capture ch.3 input (3) tin4_0 - reload timer ch.4 event input (0) rto1_1 - waveform generator ch.1 o utput pin (1) sck3_2 - multi - function serial ch.3 clock i/o (2) d a t a s h e e t 20 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 7 9 11 14 17 21 p034 - a general - purpose i/o port a06 - external bus/ address bit 6 output (0) ocu11_1 - output compare ch.11 output (1) icu2_3 - i nput capture ch.2 input (3) tin5_0 - reload timer ch.5 event input (0) rto0_1 - waveform generator ch.0 output pin (1) sot3_2 - multi - function serial ch.3 serial data output (2) - - 12 15 18 22 p150 - f general - purpose i/o port sot8_0/ sda8 - multi - function serial ch.8 serial data output (0)/ i 2 c bus serial data i/o ocu10_1 - output compare ch.10 output (1) trg6_0 - ppg trigger 6 input (0) icu1_3 - input capture ch.1 input (3) tin6_0 - reload timer ch.6 event input (0) 8 10 13 16 19 23 p151 - f general - purpose i/o port sck8_0/ scl8 - multi - function serial ch.8 clock i/o (0)/ i 2 c bus serial clock i/o ocu9_1 - output compare ch.9 output (1) trg7_0 - ppg trigger 7 input (0) icu0_3 - input capture ch.0 input (3) tin7_0 - reload timer ch.7 event input (0) zin0_2 - u/d counter ch.0 zin input (2) dtti_1 - waveform generator ch.1 input pin (1) 9 11 14 17 20 24 p035 - i general - purpose i/o port a07 - external bus/ address bit 7 output sin8_0 - multi - function serial ch.8 serial data input (0) ocu8_1 - output compare ch.8 output (1) tot4_0 - reload timer ch.4 output (0) ain0_0 - u/d counter ch.0 ain input (0) int11_0 - int11 external interrupt input (0) 10 12 15 18 21 25 p036 - a general - purpose i/o port a08 - external bus/ address bit 8 output (0) scs8_0 - serial chip select 8 i/o (0) ocu7_1 - output compare ch.7 output (1) tot5_0 - reload timer ch.5 output (0) bin0_0 - u/d counter ch.0 bin input (0) - - 16 19 22 26 p037 - a general - purpose i/o port a09 - external bus/ address bit 9 output (0) ocu6_1 - output compare ch.6 output (1) tot6_0 - reload timer ch.6 output (0) zin0_0 - u/d counter ch.0 zin input (0) - - - - - 27 p174 - a general - purpose i/o port trg8_1 - ppg trigger 8 input (1) - - - - - 28 p175 - a general - purpose i/o port trg9_1 - ppg trigger 9 input (1) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 21 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 11 13 17 20 23 29 p040 - a general - purpose i/o port a10 - external bus/ address bit 10 output (0) ppg23_1 - ppg ch.23 output (1) tot7_0 - reload timer ch.7 output (0) ain1_0 - u/d counter ch.1 ain input (0) sin0_1 - multi - function serial ch.0 serial data input (1) 12 14 18 21 24 30 p041 - i general - purpose i/o port a11 - external bus/ address bit 11 output (0) sin9_0 - multi - function serial ch.9 serial data input (0) icu9_1 - input cap ture ch.9 input (1) bin1_0 - u/d counter ch.1 bin input (0) int12_0 - int12 external interrupt input (0) 13 15 19 22 25 31 p042 - b general - purpose i/o port a12 - external bus/ address bit 12 output sot9_0 - multi - function s erial ch.9 serial data output (0) an47 - adc analog 47 input icu8_1 - input capture ch.8 input (1) trg0_1 - ppg trigger 0 input (1) zin1_0 - u/d counter ch.1 zin input (0) - - 20 23 26 32 p043 - a general - purpose i/o port a13 - external bus/ address bit 13 output (0) icu7_1 - input capture ch.7 input (1) trg1_1 - ppg trigger 1 input (1) - 16 21 24 27 33 p044 - a general - purpose i/o port a14 - external bus/ address bit 14 output (0) scs9_0 - serial chip select 9 i/o (0) icu6_1 - input capture ch.6 input (1) trg2_1 - ppg trigger 2 input (1) 14 17 22 25 28 34 p045 - g general - purpose i/o port a15 - external bus/ address bit 15 output (0) sck9_0 - multi - function serial ch.9 clock i/o (0) an46 - adc analog 46 input icu5_1 - input capture ch.5 input (1) trg3_1 - ppg trigger 3 input (1) tot1_2 - reload timer ch.1 output (2) - - - 26 29 35 p046 - a general - purpose i/o port a16 - external bus/ address bit 16 output (0) icu4_1 - input capture ch.4 input (1) trg4_1 - ppg trigger 4 input (1) - - - - - 36 p176 - a general - purpose i/o port trg10_0 - ppg trigger 10 input (0) d a t a s h e e t 22 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 15 18 23 27 30 37 p 047 - b general - purpose i/o port a17 - external bus/ address bit 17 output (0) an45 - adc analog 45 input trg8_0 - ppg trigger 8 input (0) tin3_2 - reload timer ch.3 event input (2) sot0_1 - multi - function serial ch.0 serial data output (1) - - - - - 38 p177 - a general - purpose i/o port trg11_0 - ppg trigger 11 input (0) - - - 28 31 39 p050 - a general - purpose i/o port a18 - external bus/ address bit 18 output trg5_1 - ppg trigger 5 input (1) ppg33_0 - ppg ch.33 output (0) - - - - 32 40 p051 - a general - purpose i/o port a19 - external bus/ address bit 19 output trg9_0 - ppg trigger 9 input (0) - - - - 33 41 p052 - a general - purpose i/o port a20 - external bus/ add ress bit 20 output ppg34_0 - ppg ch.34 output (0) int14_0 - int14 external interrupt input (0) 16 19 24 29 34 42 p053 - b general - purpose i/o port a21 - external bus/ address bit 21 output an44 - adc analog 44 input ppg35_0 - ppg ch.35 output (0) int14_1 - int14 external interrupt input (1) sck0_1 - multi - function serial ch.0 clock i/o (1) - - - - 35 43 p054 - a general - purpose i/o port sysclk - external bus/ s ystem clock output ppg36_ 0 - ppg ch.36 output (0) 17 22 27 32 38 46 p055 - g general - purpose i/o port cs2x - external bus chip select 2 output (0) sin10_0 - multi - function serial ch.10 serial data input (0) an43 - adc analog 43 input ppg37_0 - pp g ch.37 output (0) tin4_1 - reload timer ch.4 event input (1) - - - - - 47 p180 - a general - purpose i/o port ppg40_0 - ppg ch.40 output (0) - - - - - 48 p181 - a general - purpose i/o port ppg41_0 - ppg ch.41 output (0) - - - 33 39 49 p056 - a general - purpose i/o port cs3x - external bus chip select 3 output (0) icu9_0 - input capture ch.9 input (0) ppg0_1 - ppg ch.0 output (1) icu0_1 - input capture ch.0 input (1) tin5_1 - reload timer ch.5 e vent input (1) dtti_2 - waveform generator ch.0 - ch.5 input pin (2) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 23 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 19 24 29 35 41 51 p057 - g general - purpose i/o port rdy - external bus/ready input (0) sck10_1 - multi - function serial ch.10 clock i/o (1) an42 - adc analog 42 input icu8_0 - input capture ch.8 input (0) trg0_2 - ppg trigger 0 input (2) ppg1_1 - ppg ch.1 output (1) icu1_1 - input capture ch.1 input (1) tin6_1 - reload timer ch.6 event input (1) - - - - 44 5 4 p142 - f general - purpose i/o port sck10_0/ scl10 - multi - function serial ch.10 clock i/o (0)/ i 2 c bus serial clock i/o ppg38_0 - ppg ch.38 output (0) tin7_1 - reload timer ch.7 event input (1) - - - - 45 55 p143 - f general - purp ose i/o port sot10_0/ sda10 - multi - function serial ch.10 serial data output (0)/ i 2 c bus serial data i/o ppg39_0 - ppg ch.39 output (0) tot4_1 - reload timer ch.4 output (1) - - - - - 56 p182 - a general - purpose i/o port pp g42_0 - ppg ch.42 output (0) - - 32 38 46 57 p060 - a general - purpose i/o port scs10_0 - serial chip select 10 i/o (0) ppg2_1 - ppg ch.2 output (1) icu2_1 - input capture ch.2 input (1) tot5_1 - reload timer ch.5 output (1 ) int13_0 - int13 external interrupt input (0) 22 27 33 39 47 58 p061 - b general - purpose i/o port sot10_1 - multi - function serial ch.10 serial data output (1) an41 - adc analog 41 input icu6_0 - input capture ch.6 input (0) ppg3_1 - ppg ch.3 output (1) icu3_1 - input capture ch.3 input (1) tot6_1 - reload timer ch.6 output (1) int13_1 - int13 external interrupt input (1) 23 28 34 40 48 59 p062 - b general - purpose i/o port scs10_1 - serial chip select 10 i/o (1) scs40_0 - serial chip select 40 i/o (0) an40 - adc analog 40 input ppg4_1 - ppg ch.4 output (1) frck0_0 - free - run timer 0 clock input (0) tot7_1 - reload timer ch.7 output (1) zin1_1 - u/d counter ch.1 zin input (1) d a t a s h e e t 24 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - 29 35 41 49 60 p063 - b general - purpose i/o port scs41_0 - serial chip select 41 output (0) an39 - adc analog 39 input ppg5_1 - ppg ch.5 output (1) frck1_0 - free - ru n timer 1 clock input (0) bin1_1 - u/d counter ch.1 bin input (1) - - - - - 61 p183 - a general - purpose i/o port ppg43_0 - ppg ch.43 output (0) 24 30 36 42 50 62 p064 - b general - purpose i/o port scs42_0 - serial chip select 42 ou tput (0) an38 - adc analog 38 input frck2_0 - free - run timer 2 clock input (0) ain1_1 - u/d counter ch.1 ain input (1) ppg43_1 - ppg ch.43 output (1) - - 37 43 51 63 p065 - a general - purpose i/o port scs43_0 - seri al chip select 43 output (0) frck3_0 - free - run timer 3 clock input (0) zin0_1 - u/d counter ch.0 zin input (1) ppg44_1 - ppg ch.44 output (1) - - - - - 64 p184 - a general - purpose i/o port ppg44_0 - ppg ch.44 output (0) - - - - - 65 p185 - a general - purpose i/o port ppg45_0 - ppg ch.45 output (0) 25 31 38 44 52 66 p066 - b general - purpose i/o port sot4_2 - multi - function serial ch.4 serial data output (2) scs3_0 - serial chip select 3 i/o (0) an37 - adc analog 37 input frck4_0 - free - run timer 4 clock input (0) bin0_1 - u/d counter ch.0 bin input (1) - 32 39 45 53 67 p067 - b general - purpose i/o port an36 - adc analog 36 input frck5_0 - free - run timer 5 cl ock input (0) ain0_1 - u/d counter ch.0 ain input (1) - - 40 46 54 68 p070 - a general - purpose i/o port icu0_2 - input capture ch.0 input (2) 26 33 41 47 55 69 p071 - g general - purpose i/o port sck4_2 - multi - function serial ch.4 clock i/o (2) an35 - adc analog 35 input icu1_2 - input capture ch.1 input (2) monclk - clock monitor output pin d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 25 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 27 34 42 48 56 70 p072 - g general - purpose i/o port sin4_0 - multi - function serial ch.4 seri al data input (0) an34 - adc analog 34 input icu2_2 - input capture ch.2 input (2) int5_0 - int5 external interrupt input (0) - 35 43 49 57 71 p073 - d general - purpose i/o port sot4_0/ sda4 - multi - function serial ch.4 ser ial data output (0)/i 2 c bus serial data i/o an33 - adc analog 33 input icu3_2 - input capture ch.3 input (2) - - - - - 72 p186 - a general - purpose i/o port ppg46_0 - ppg ch.46 output (0) - - - - - 73 p187 - a general - purpose i/o port ppg47_0 - ppg ch.47 output (0) - - - 50 58 74 p074 - e general - purpose i/o port sck4_0/ scl4 - multi - function serial ch.4 clock i/o (0)/ i 2 c bus serial clock i/o - - - 51 59 75 p075 - f general - purpose i/o port sin3_0 - mul ti - function serial ch.3 serial data input (0) int4_0 - int4 external interrupt input (0) - - - 52 60 76 p076 - e general - purpose i/o port sot3_0/ sda3 - multi - function serial ch.3 serial data output (0)/ i 2 c bus serial data i/o - - - 53 6 1 77 p077 - e general - purpose i/o port sck3_0/ scl3 - multi - function serial ch.3 clock i/o (0)/ i 2 c bus serial clock i/o - - 44 54 62 78 p152 - a general - purpose i/o port scs53_0 - serial chip select 53 output (0) 28 36 45 55 63 79 p153 - g general - purpose i/o port sck5_0/ scl5 - multi - function serial ch.5 clock i/o (0)/ i 2 c bus serial clock i/o an32 - adc analog 32 input frck1_1 - free - run timer 1 clock input (1) int4_1 - int4 external interrupt input (1 ) - - - - 64 80 p080 - a general - purpose i/o port scs52_0 - serial chip select 52 output (0) ppg0_0 - ppg ch.0 output (0) 29 37 46 56 65 81 p081 - g general - purpose i/o port sot5_0/ sda5 - multi - function serial ch.5 serial data ou tput (0)/ i 2 c bus serial data i/o an0 - adc analog 0 input ppg1_0 - ppg ch.1 output (0) 30 38 47 57 66 82 p082 - g general - purpose i/o port sin5_0 - multi - function serial ch.5 serial data input (0) an1 - adc analog 1 input ppg2_0 - ppg ch.2 output (0) d a t a s h e e t 26 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - - - 67 83 p083 - b general - purpose i/o port scs50_0 - serial chip select 50 i/o (0) an2 - adc analog 2 input ppg3_0 - ppg ch.3 output (0) - - - - 68 84 p084 - b general - purpo se i/o port scs51_0 - serial chip select 51 output (0) an3 - adc analog 3 input ppg4_0 - ppg ch.4 output (0) - - - - 69 85 p085 - a general - purpose i/o port ppg5_0 - ppg ch.5 output (0) - - 48 58 70 86 p086 - c general - pu rpose i/o port dao1 - dac analog 1 output ppg6_0 - ppg ch.6 output (0) 31 39 49 59 71 87 p087 - c general - purpose i/o port dao0 - dac analog 0 output ppg7_0 - ppg ch.7 output (0) int8_0 - int8 external interrupt i nput (0) - - - - - 90 p190 - a general - purpose i/o port tin0_1 - reload timer ch.0 event input (1) - - - - - 91 p191 - a general - purpose i/o port tin1_1 - reload timer ch.1 event input (1) - - - - 74 92 p090 - b general - purpose i/o port an4 - adc analog 4 input icu0_0 - input capture ch.0 input (0) tin2_1 - reload timer ch.2 event input (1) - - - - 75 93 p091 - b general - purpose i/o port an5 - adc analog 5 input ppg41_1 - ppg ch.41 output (1) icu1_0 - input capture ch.1 input (0) tin3_1 - reload timer ch.3 event input (1) - - - - 76 94 p092 - b general - purpose i/o port an6 - adc analog 6 input ppg40_1 - ppg ch.40 output (1) icu2_0 - input capture ch.2 inpu t (0) tot0_1 - reload timer ch.0 output (1) - - - - - 95 p192 - a general - purpose i/o port ppg24_1 - ppg ch.24 output (1) tot1_1 - reload timer ch.1 output (1) 34 42 52 62 77 96 p093 - j general - purpose i/o port tx0_1 - ca n transmission data 0 output (1) sin11_0 - multi - function serial ch.11 serial data input (0) an7 - adc analog 7 input icu4_2 - input capture ch.4 input (2) ppg16_1 - ppg ch.16 output (1) icu3_0 - input capture ch.3 input (0) tot2_1 - reload timer ch.2 output (1) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 27 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - - - 78 97 p094 - b general - purpose i/o port an8 - adc analog 8 input icu4_0 - input capture ch.4 input (0) tot3_1 - reload timer ch.3 output (1) - - 53 63 79 98 p095 - b general - purpose i/o port tx0(128) - can transmission data 0 output scs11_0 - serial chip select 11 i/o (0) an9 - adc analog 9 input 35 43 54 64 80 99 p096 - g general - purpose i/o port rx0(128) - can reception data 0 inpu t sot11_0/ sda11 - multi - function serial ch.11 serial data output (0)/ i 2 c bus serial data i/o an10 - adc analog 10 input int0_0 - int0 external interrupt input (0) 36 44 55 65 81 100 p097 - g general - purpose i/o port sck1 1_0/ scl11 - multi - function serial ch.11 clock i/o (0)/ i 2 c bus serial clock i/o an11 - adc analog 11 input icu5_0 - input capture ch.5 input (0) ppg17_1 - ppg ch.17 output (1) - 48 59 69 85 104 p100 - g general - purpose i/o port sck7_0/ scl7 - multi - function serial ch.7 clock i/o (0)/ i 2 c bus serial clock i/o an12 - adc analog 12 input ppg8_0 - ppg ch.8 output (0) - - 60 70 86 105 p101 - g general - purpose i/o port sot7_0/ sda7 - multi - function s erial ch.7 serial data output (0)/ i 2 c bus serial data i/o an13 - adc analog 13 input ppg9_0 - ppg ch.9 output (0) 40 49 61 71 87 106 p102 - g general - purpose i/o port sin7_0 - multi - function serial ch.7 serial data input (0) an14 - adc analog 14 input ppg10_0 - ppg ch.10 output (0) int10_0 - int10 external interrupt input (0) 41 50 62 72 88 107 p103 - h general - purpose i/o port scs73_0 - serial chip select 73 output (0) an15 - adc analog 1 5 input ppg11_0 - ppg ch.11 output (0) 42 51 63 73 89 108 p104 - h general - purpose i/o port scs72_0 - serial chip select 72 output (0) an16 - adc analog 16 input ppg12_0 - ppg ch.12 output (0) 43 52 64 74 90 109 p105 - h general - purpose i/o port scs71_0 - serial chip select 71 output (0) an17 - adc analog 17 input ppg13_0 - ppg ch.13 output (0) d a t a s h e e t 28 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - 65 75 91 110 p106 - h general - purpose i/o port scs70_0 - serial chip select 70 i /o (0) an18 - adc analog 18 input ppg14_0 - ppg ch.14 output (0) - 53 66 76 92 111 p107 - b general - purpose i/o port an19 - adc analog 19 input ppg15_0 - ppg ch.15 output (0) - - - - - 112 p193 - a general - purpose i/o po rt ppg25_1 - ppg ch.25 output (1) - - - 77 93 113 p154 - b general - purpose i/o port an20 - adc analog 20 input - - - 78 94 114 p155 - b general - purpose i/o port an21 - adc analog 21 input 44 54 67 79 95 115 nmix n m non - masking interrupt input 45 55 68 80 96 116 p110 - b general - purpose i/o port tx1(64) - can transmission data 1 output scs63_0 - serial chip select 63 output (0) an22 - adc analog 22 input - - 69 81 97 117 p111 - g general - purpose i/o port rx1(64) - can reception data 1 input scs62_0 - serial chip select 62 output (0) an23 - adc analog 23 input int1_0 - int1 external interrupt input (0) - - - 82 98 118 p112 - b general - purpose i/o port an24 - a dc analog 24 input ppg16_0 - ppg ch.16 output (0) rto0_0 - waveform generator ch. 0 output pin (0) - - - 83 99 119 p113 - b general - purpose i/o port an25 - adc analog 25 input ppg17_0 - ppg ch.17 output (0) rto1_0 - waveform generator ch. 1 output pin (0) - - - - - 120 p194 - a general - purpose i/o port frck5_1 - free - run timer 5 clock input (1) ppg26_1 - ppg ch.26 output (1) - - - - - 121 p195 - a general - purpose i/o port frck4_1 - free - ru n timer 4 clock input (1) ppg27_1 - ppg ch.27 output (1) - 56 70 84 100 122 p114 - b general - purpose i/o port scs61_0 - serial chip select 61 output (0) an26 - adc analog 26 input ppg18_0 - ppg ch.18 output (0) rto2 _0 - waveform generator ch.2 output pin (0) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 29 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 46 57 71 85 101 123 p115 - g general - purpose i/o port rx1_1 - can reception data 1 input (1) sot6_0/ sda6 - multi - function serial ch.6 serial data output (0)/i 2 c bus serial data i /o an27 - adc analog 27 input ppg19_0 - ppg ch.19 output (0) rto3_0 - waveform generator ch.3 output pin (0) int1_1 - int1 external interrupt input (1) 47 58 72 86 102 124 p116 - g general - purpose i/o port sck6_0/ scl6 - multi - function serial ch.6 clock i/o (0)/ i 2 c bus serial clock i/o an28 - adc analog 28 input ppg20_0 - ppg ch.20 output (0) rto4_0 - waveform generator ch.4 output pin (0) - - 73 87 103 125 p117 - b general - purpose i/o p ort scs60_0 - serial chip select 60 i/o (0) an29 - adc analog 29 input ppg21_0 - ppg ch.21 output (0) rto5_0 - waveform generator ch.5 output pin (0) - - - - - 126 p196 - a general - purpose i/o port frck3_1 - free - r un timer 3 clock input (1) ppg28_1 - ppg ch.28 output (1) - - - 88 104 127 p120 - b general - purpose i/o port an30 - adc analog 30 input ocu6_0 - output compare ch.6 output (0) ppg22_0 - ppg ch.22 output (0) int9_0 - int9 external interrupt input (0) - - - - 105 128 p121 - a general - purpose i/o port ocu7_0 - output compare ch.7 output (0) ppg23_0 - ppg ch.23 output (0) 48 59 74 89 106 129 p122 - j general - purpose i/o port sin6_0 - multi - func tion serial ch.6 serial data input (0) an31 - adc analog 31 input ocu8_0 - output compare ch.8 output (0) int9_1 - int9 external interrupt input (1) - - - - - 130 p197 - a general - purpose i/o port ppg29_1 - ppg ch.29 outpu t (1) - - - - 107 131 p123 - a general - purpose i/o port ocu9_0 - output compare ch.9 output (0) 49 62 77 92 110 134 debugif - l mdi i/o for d ebugger (ocd) - - - - - 135 p160 - a general - purpose i/o port ppg30_1 - ppg ch.30 output (1) - - - - - 136 p161 - a general - purpose i/o port ppg31_1 - ppg ch.31 output (1) - - - - 111 137 p124 - a general - purpose i/o port ocu10_0 - output compare ch.10 output (0) d a t a s h e e t 30 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - - 93 112 138 p125 - a general - purpose i/o port ocu11_0 - output compare ch.11 output (0) 50 63 78 94 113 139 p126 - f general - purpose i/o port sin0_0 - multi - function serial ch.0 serial data input (0) int6_0 - int6 external interrupt input (0) - 64 79 95 114 140 p127 - a general - pur pose i/o port sot0_0 - multi - function serial ch.0 serial data output (0) - - 80 96 115 141 p130 - f general - purpose i/o port sck0_0 - multi - function serial ch.0 clock i/o (0) - - - - - 142 p162 - a general - purpose i/o port trg5_2 - ppg trigger 5 input (2) - - - - - 143 p163 - a general - purpose i/o port trg6_2 - ppg trigger 6 input (2) 51 65 81 97 116 144 md0 - k mode pin 0 52 66 82 98 117 145 md1 - k mode pin 1 53 67 83 99 118 146 x0 - n main clock oscillation input 54 68 84 100 119 147 x1 - n main clock oscillation output 56 70 86 102 121 149 p135 - a general - purpose i/o port dtti_0 - waveform generator ch.0 - ch.5 input pin (0) x1a - o sub clock oscillation output 57 71 87 103 122 150 p136 - a general - p urpose i/o port x0a - o sub clock oscillation input 58 72 88 104 123 151 rstx n m external reset input - - - - 124 152 p131 - a general - purpose i/o port adtg0_0 - a/d converter external trigger input 0 (0) - - - 105 125 153 p132 - a gener al - purpose i/o port scs1_0 - serial chip select 1 i/o (0) adtg1_0 - a/d converter external trigger input 1 (0) - - 89 106 126 154 p133 - a general - purpose i/o port tx2(64) - can transmission data 2 output - - 90 107 127 155 p134 - f general - purpose i/o port rx2(64) - can reception data 2 input scs1_1 - serial chip select 1 i/o (1) icu7_0 - input capture ch.7 input (0) int7_0 - int7 external interrupt input (0) - - 91 108 128 156 p144 - f general - p urpose i/o port sck1_1 - multi - function serial ch.1 clock i/o (1) - - 94 111 131 159 p000 - f general - purpose i/o port d16 - external bus data bit16 i/o (0) sin1_0 - multi - function serial ch.1 serial data input (0) tioa0_1 - tioa output of base timer ch.0 (1) int2_0 - int2 external interrupt input (0) - 75 95 112 132 160 p001 - a general - purpose i/o port d17 - external bus data bit17 i/o sot1_0 - multi - function serial ch.1 serial data output (0) tioa1_1 - tioa i/o of base timer ch.1 (1) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 31 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - - 113 133 161 p002 - f general - purpose i/o port d18 - external bus data bit18 i/o sck1_0 - multi - function serial ch.1 clock i/o (0) tiob0_1 - tiob input of base timer ch.0 (1) - 76 96 114 134 162 p003 - f general - purpose i/o port d19 - external bus data bit19 i/o sin2_0 - multi - function serial ch.2 serial data input (0) tiob1_1 - tiob input of base timer ch.1 (1) int3_0 - int3 external interrupt in put (0) - - - - 135 163 p004 - a general - purpose i/o port d20 - external bus data bit20 i/o (0) sot2_0 - multi - function serial ch.2 serial data output (0) - - - - - 164 p164 - a general - purpose i/o port ppg32_1 - ppg ch.32 output (1) 61 77 97 115 136 165 p005 - f general - purpose i/o port d21 - external bus data bit21 i/o (0) sck2_0 - multi - function serial ch.2 clock i/o (0) adtg0_1 - a/d converter external trigger input 0 (1) int7_1 - int7 external interrupt input (1) (rx2(64)) - (can reception data 2 input mb91f52 xb ,mb91f52xd only) - - - - - 166 p165 - a general - purpose i/o port ppg33_1 - ppg ch.33 output (1) 62 78 98 116 137 167 p006 - a general - purpose i/o port d22 - ext ernal bus data bit22 i/o (0) scs2_0 - serial chip select 2 i/o (0) adtg1_1 - a/d converter external trigger input 1 (1) int2_1 - int2 external interrupt input (1) (tx2(64)) - (can transmission data 2 output mb91f52 xb ,mb91f5 2xd only) - - - 117 138 168 p007 - a general - purpose i/o port d23 - external bus data bit23 i/o - - - - - 169 p166 - a general - purpose i/o port ppg34_1 - ppg ch.34 output (1) - - - 118 139 170 p010 - a general - purpose i/o port d2 4 - external bus data bit24 i/o 63 79 99 119 140 171 p011 - a general - purpose i/o port wot - rtc output signal d25 - external bus data bit25 i/o sot2_1 - multi - function serial ch.2 serial data output (1) tioa0_0 - tioa o utput of base timer ch.0 (0) int3_1 - int3 external interrupt input (1) - - - - 141 172 p012 - a general - purpose i/o port d26 - external bus data bit26 i/o tiob0_0 - tiob input of base timer ch.0 (0) - - - - - 173 p167 - a genera l - purpose i/o port ppg35_1 - ppg ch.35 output (1) d a t a s h e e t 32 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential pin no. pin name pola rity i/o circuit types * 1 function * 2 64 80 100 120 144 176 - - - - 142 174 p013 - a general - purpose i/o port d27 - external bus data bit27 i/o tioa1_0 - tioa i/o of base timer ch.1 (0) - - - - 143 175 p014 - a general - purpose i/o port d28 - external bus data bit28 i/o tiob1_0 - tiob input of base timer ch.1 (0) 18 23 28 34 40 50 avcc1 - - a nalog power supply for ad/da convertor unit1 39 47 58 68 84 103 avcc0 - - a nalog power supply for ad/da convertor unit0 20 25 30 3 6 42 52 avrh1 - - upper limit reference voltage for ad convertor unit1 38 46 57 67 83 102 avrh0 - - upper limit reference voltage for ad convertor unit0 21 26 31 37 43 53 avss1/ avrl1 - - gnd for ad/da convertor unit1 lower limit reference voltage for ad convertor unit1 37 45 56 66 82 101 avss0/ avrl0 - - gnd for ad/da convertor unit0 lower limit reference voltage for ad convertor unit0 60 74 93 110 130 158 c - - external capacity connection output - 20 25 30 36 44 vcc - - +5.0 v power supply 32 40 50 60 72 88 - 61 76 91 109 133 64 80 100 120 144 176 1 1 1 1 1 1 vss - - gnd - 21 26 31 37 45 33 41 51 61 73 89 - 60 75 90 108 132 55 69 85 101 120 148 59 73 92 109 129 157 *1: for the i/o circuit types, see " ? i/o circ uit type " . *2: for switching, see " i/o port" in hardware manual. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 33 confidential ? i/o circuit type type c ircuit remarks a ?general - purpose i/o port ?output 4ma ?pull - up resistor control 50k ?automotive input b ?analo g input , general - purpose i/o port ?output 4ma ?pull - up resistor control 50k ?automotive input c ?dac output , general - purpose i/o port ?output 4ma ?pull - up resistor control 50k ?automotive input d ?i 2 c analog input , general - purpose i/o port ?output 3ma ?pull - up resistor control 50k ?i 2 c hysteresis input pull - up control d i gital output d i gital output standby control i 2 c input analog input pull - up control d i gital output d i gital output standby control automotive input dac output pull - up control d i gital output d i gital output standby control aut omotive input analog input pull - up control d i gital output d i gital output standby control automotive input d a t a s h e e t 34 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confide ntial type c ircuit remarks e ?i 2 c,general - purpose i/o port ?output 3ma ?pull - up resistor control 50k ?i 2 c hysteresis input f ?general - purpose i/o port ?output 4ma ?pull - up resistor control 50k ? cmos hysteresis input g ?analog input , general - purpose i/o port ?output 4ma ?pull - up resistor control 50k ? cmos hysteresi s input h ?analog input , general - purpose i/o port ?output 12ma ?pull - up resistor control 50k ?automotive input pull - up control d i gital output d i gital output standby control automotive input analog input pull - up control d i gital output d i gital output standby control cmos - hys input analog input pull - up control d i gital output d i gital output standby control cmos - hys input pull - up control d i gital output d i gital output standby control i 2 c input d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 35 confidential type c ircuit remarks i ? 3v pad power supply (5v tolerant) , general - purpose i/o port ?output 4ma ? cm os hysteresis input j ? 3v pad power supply (5v tolerant) , analog input , general - purpose i/o port ?output 4ma ? cmos hysteresis input k ?mode i/o ? cmos hysteresis input l ?open - drain i/o ?output 25ma (nod) ?ttl input ttl input d i gital output control mode input d i gital output d i gital output standby control cmos - hys input analog input d i gital output d i gital output standby control cmos - hys input d a t a s h e e t 36 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confide ntial type c ircuit remarks m ? cmos hysteresis input ?pull - up resistor 50k (5v cont) n ?main oscillation i/o o ?sub oscillation i/o standby control input standby control input cmos - hy s input d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 37 confidential ? handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes prec autions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product design this section describes precautions when designing electronic equipment using semicondu ctor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? re commended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within t he recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. user s considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power s upply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to perma nent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large curren t flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of op eration. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high volta ges, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of lat ch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute ma ximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 2 e a d a t a s h e e t 38 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? observance of safety regulations and standards most countries in th e world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor de vices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during s oldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be don e by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liq uid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions. if socket mount ing is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased su sceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with spansion ranking of recommended conditions. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 39 confidential ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be red uced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. s tore products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c /24 h ? static elect ricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generatio n may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on t he level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hi ghly static - prone materials for storage of completed board assemblies. d a t a s h e e t 40 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to ch emical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments invol ving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. http://www.spansion.com/fjdocuments/fj/datasheet/e - ds/ds00 - 00004.pdf d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00 011 - 2 v 0 - e 41 confidential ? handling devices this section explains the latch - up prevention and pin processing. ? for latch - up prevention if a voltage higher than vcc or a voltage lower than vss is applied to an i/o pin, or if a voltage exceeding the ratings is applied between vcc and vss pins, a latch - up may occur in cmos ic. if the latch - up occurs, the power supply current increases excessively and device elements may be damaged by heat. take care to prevent any voltage from exceeding the maximum ratings in device application. also, the analog power supply (av cc , avrh) and analog input must not be exceed the digital power supply (v cc ) when the power supply to the analog system is turned on or off. in the correct power - on sequence of the microcontroller, turn on the digital power suppl y (v cc ) and analog power supplies (av cc , avrh) simultaneously. or, turn on the digital power supply (v cc ), and then turn on analog power supplies (av cc , avrh). ? treatment of unused pins if unused input pins are left open, they may cause a permanent damage t o the device due to malfunction or latch - up. connect at least a 2k resistor to each of the unused pins for pull - up or p u ll - down processing. also, if i/o pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the input pins. ? power su pply pins the device is designed to ensure that if the device contains multiple v cc or v ss pins, the pins that should be at the same potential are interconnected to prevent latch - up or other malfunctions. further, connect these pins to an external power s u pply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. as shown in f igure 1 , all vss power supply pins must be treated in the similar way. if multiple vcc or vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. figure 1 power supply input pins the power supply pins should be connected t o vcc and vss pins of this device at the low impedance from the power supply source. in the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of c pin is recommended to use as a bypass capacitor between vcc and vss pins . vss vss vcc vcc vss vcc vcc vss vss vcc d a t a s h e e t 42 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? crystal oscillation circuit an external noise to the x0 or x1 pin may cause a device malfunction. the printed circuit board must be designed to lay out x0 and x1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be gr ounded to the close position to the device. the printed circuit board artwork is recommended to surround the x0 and x1 pins by ground circuits. ? mode pins ( md1, md0 ) connec t the md1 and md0 m ode pin s to the vcc or v ss pin directly. to prevent an erroneous se lection of test mode caused by the noise, reduce the pattern length between each mode pin and vcc or vss pin on the printed circuit board. also, use the low - impedance pin connection. ? during power - on to prevent a malfunction of the voltage step - down circuit built in the device, set the voltage rising time to have 50 s or longer (between 0.2v and 2.7v) during power - on. ? notes during pll clock operation when the pll clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self - oscillator circuit built in the pll clock. this operation is not guaranteed. ? treatment of a/d converter power supply pins connect the pins to have a v cc =avrh=v cc and av ss /avrl=v ss even if the a/d converter is not used. ? no tes on using external clock an external clock is not supported. none of the external d irect clock input can be used for both main clock and sub clock . ? power - on sequence of a/d converter analog inputs be sure to turn on the dig ital power supply (v cc ) first, and then turn on the a/d converter power supplies (avcc, avrh, avrl) and analog inputs (an0 to an 47 ). also, turn off the a/d converter power supplies and analog inputs first, and then turn off the digital power supply (v cc ). when the avrh pin voltage is turned on or off, it must not exceed av cc . even if a common analog input pin is used as an input port, its input voltage must not exceed av cc . (however, the analog power supply and digital power supply can be turned on or off s imultaneously.) ? treatment of c pin this device contains a voltage step - down circuit. a capacitor must always be connected to the c pin to assure the internal stabilization of the device. for the standard values, see the "recommended operating conditions" o f the latest data sheet. note: please see the latest data sheet for a detailed specification of the operation voltage. ? function switching of a multiplexed port t o switch between the port function and the multiplexed pin function, use the pfr (port functio n register). however, if a pin is also used for an external bus, its function is switched by the external bus setting. for details, see " i/o ports" in the hardware manual . d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00 011 - 2 v 0 - e 43 confidential ? low - power consumption mode t o transit t o the sleep mode, watch mode, stop mode, wa tch mode(power - off) or stop mode(power - off), follow the procedure explained in "activating the sleep mode, watch mode, or stop mode" or "activating the watch mode (power - off) or stop mode (power - off) " of " power c onsumption control" in the hardware manual . take the following notes when using a monitor debugger. do not set a break point for the low - power consumption transition program. do not execute an operation step for the low - power consumption transition program. ? notes when writing data in a register havi ng the status flag when writing data in the register that has a status flag (especially, an interrupt request flag) to control function , tak ing care not to clear its status flag erroneously must be followed. the program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value. especially, if multiple control bits are used, the bit instruction cannot be used. (the bit instruction can access to a single bit only.) by t he byte, half - word, or word access , data is written to the control bits and status flag simultaneously. during this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. note: these points can be ignore d because the bit instructions are already taken the points into consideration . d a t a s h e e t 44 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? block diagram ? mb91f522b, mb91f523b, mb91f524b, mb91f525b, mb91f526b from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on - chip bus layer 2 peripheral bus bridge can prescaler watchdog timer(sw and hw) delay interrupt interrupt controller rtc wdt1 calibration / port setting low - power consumption setting register 16 32 wild register i / o port on - chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on - chip bus(ahb) xbs clock control clock setting, main timer, sub timer, pll timer m p u 32bit peripheral bus (apb) clock control divide control bus performance counter 16bit peripheral bus backup ram +8kb timing protection unit ppg(21ch) reload timer (7ch) 8bit da converter (1ch) external interrupt input(16ch) 32bit output compare(4ch) base timer (1ch) u/d counter (2ch) 32bit free - run timer (1ch) 32bit input capture (5ch) multi - function serial interface (8ch) dmac (16 ch) can (2ch) crc operation mode register wave generator (6ch) 12bit ad converter (13ch + 13ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low - voltage detection external power supply low - voltage detection reset control register nmi flash ? main flash 256k/384k/512k/768k/ 1024kb +64kb ? workflash 64kb ram 48k/64k/96k/128k clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low - voltage detection internal power supply low - voltage detection rstx nmix md0,md1,p006 rx,tx frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto d a t a s h e e t jan uary 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 45 confidential ? mb91f522d, mb91f523d, mb91f524d, mb91f525d, MB91F526D from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on - chip bus layer 2 peripheral bus bridge can prescaler watchdog timer(sw and hw) delay interrupt interrupt controller rtc wdt1 calibration / port setting low - power consumption setting register 16 32 wild register i / o port on - chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on - chip bus(ahb) xbs clock control clock setting, main timer, sub timer, pll timer m p u 32bit peripheral bus (apb) clock control divide control bus performance counter 16bit peripheral bus backup ram +8kb timing protection unit ppg(27ch) reload timer (7ch) 8bit da converter (2ch) external interrupt input(16ch) 32bit output compare(4ch) base timer (1ch) u/d counter (2ch) 32bit free - run timer (2ch) 32bit input capture (5ch) multi - function serial interface (9ch) dmac (16 ch) can (2ch) crc operation mode register wave generator (6ch) 12bit ad converter (21ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low - voltage detection external power supply low - voltage detection reset control register nmi flash ? main flash 256k/384k/512k/768k/ 1024kb +64kb ? workflash 64kb ram 48k/64k/96k/128k clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low - voltage detection internal power supply low - voltage detection rstx nmix md0,md1,p006 rx,tx frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto d a t a s h e e t 46 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? mb91f522f, mb91f523f, mb91f524f, mb91f525f, mb91f526f from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on - chip bus layer 2 peripheral bus bridge can prescaler watchdog timer(sw and hw) delay interrupt interrupt controller rtc wdt1 calibration / port setting low - power consumption setting register 16 32 wild register i / o port on - chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on - chip bus(ahb) xbs clock control clock setting, main timer, sub timer, pll timer m p u 32bit peripheral bus (apb) clock control divide control bus performance counter 16bit peripheral bus backup ram +8kb timing protection unit ppg(34ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input(16ch) 32bit output compare(6ch) base timer (1ch) u/d counter (2ch) 32bit free - run timer (3ch) 32bit input capture (6ch) multi - function serial interface (12ch) dmac (16 ch) can (3ch) crc operation mode register wave generator (6ch) 12bit ad converter (21ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low - voltage detection external power supply low - voltage detection reset control register nmi flash ? main flash 256k/384k/512k/768k/ 1024kb +64kb ? workflash 64kb ram 48k/64k/96k/128k clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low - voltage detection internal power supply low - voltage detection rstx nmix md0,md1,p006 rx,tx frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto d a t a s h e e t jan uary 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 47 confidential ? mb91f522j, mb91f523j, mb91f524j, mb91f525j, mb91f526j from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on - chip bus layer 2 peripheral bus bridge can prescaler watchdog timer(sw and hw) delay interrupt interrupt controller rtc wdt1 calibration / port setting low - power consumption setting register 16 32 wild register i / o port on - chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on - chip bus(ahb) xbs clock control clock setting, main timer, sub timer, pll timer m p u 32bit peripheral bus (apb) clock control divide control bus performance counter 16bit peripheral bus backup ram +8kb timing protection unit ppg(38ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input(16ch) 32bit output compare(6ch) base timer (2ch) u/d counter (2ch) 32bit free - run timer (3ch) 32bit input capture (6ch) multi - function serial interface (12ch) dmac (16 ch) can (3ch) crc operation mode register wave generator (6ch) 12bit ad converter (26ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low - voltage detection external power supply low - voltage detection reset control register nmi flash ? main flash 256k/384k/512k/768k/ 1024kb +64kb ? workflash 64kb ram 48k/64k/96k/128k clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low - voltage detection internal power supply low - voltage detection rstx nmix md0,md1,p006 rx,tx frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto d a t a s h e e t 48 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? mb91 f522k, mb91f523k, m b91f524k, mb91f525k, mb91f526k from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on - chip bus layer 2 external bus i / f peripheral bus bridge can prescaler watchdog timer(sw and hw) delay interrupt interrupt controller rtc wdt1 calibration / port setting low - power consumption setting register 16 32 wild register i / o port on - chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on - chip bus(ahb) xbs clock control clock setting, main timer, sub timer, pll timer m p u 32bit peripheral bus (apb) clock control divide control bus performance counter 16bit peripheral bus backup ram +8kb timing protection unit ppg(44ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input(16ch) 32bit output compare(6ch) base timer (2ch) u/d counter (2ch) 32bit free - run timer (3ch) 32bit input capture (6ch) multi - function serial interface (12ch) dmac (16 ch) can (3ch) crc operation mode register wave generator (6ch) 12bit ad converter (32ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low - voltage detection external power supply low - voltage detection reset control register nmi flash ? main flash 256k/384k/512k/768k/ 1024kb +64kb ? workflash 64kb ram 48k/64k/96k/128k clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low - voltage detection internal power supply low - voltage detection rstx nmix md0,md1,p006 rx,tx d,a, asx,cs, rdx, wrx, sysclk, rdy frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto bus bridge (32bit < - > 16bit) d a t a s h e e t jan uary 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 49 confidential ? mb91f522l, mb91f523l, mb91f524l, mb91f525l, mb91f526l from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on - chip bus layer 2 external bus i / f peripheral bus bridge can prescaler watchdog timer(sw and hw) delay interrupt interrupt controller rtc wdt1 calibration / port setting low - power consumption setting register 16 32 wild register i / o port on - chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on - chip bus(ahb) xbs clock control clock setting, main timer, sub timer, pll timer m p u 32bit peripheral bus (apb) clock control divide control bus performance counter 16bit peripheral bus backup ram +8kb timing protection unit ppg(48ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input(16ch) 32bit output compare(6ch) base timer (2ch) u/d counter (2ch) 32bit free - run timer (3ch) 32bit input capture (6ch) multi - function serial interface (12ch) dmac (16 ch) can (3ch) crc operation mode register wave generator (6ch) 12bit ad converter (32ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low - voltage detection external power supply low - voltage detection reset control register nmi flash ? main flash 256k/384k/512k/768k/ 1024kb +64kb ? workflash 64kb ram 48k/64k/96k/128k clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low - voltage detection internal power supply low - voltage detection rstx nmix md0,md1,p006 rx,tx d,a, asx,cs, rdx, wrx, sysclk, rdy frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto d a t a s h e e t 50 mb91f526l_ds705 - 00011 - 2 v 0 - e, j anuary 31, 2014 confidential ? memory map ? mb91f522, mb91f523, mb91f524 mb91f5 2 2 mb91f52 3 mb91f52 4 0000 0000 h i/o 0000 0000 h i/o 0000 0000 h i/o 0000 4000 h backup ram (8kb) 0000 4000 h backup ram (8kb) 0000 4000 h backup ram (8kb) 0000 6000 h i/o 0000 6000 h i/o 0000 6000 h i/o 0001 0000 h ram (48kb) 0001 0000 h ram (48kb) 0001 0000 h ram (64kb) 0001 c000 h 000 1 c000 h 0002 0000 h 0007 0000 h flash memory 0007 0000 h 0007 0000 h (256+64)kb flash memory flash memory (384+64)kb (512+64)kb 000c 0000 h 000e 0000 h 0010 0000 h 0033 0000 h workflash 0033 0000 h workflash 0033 0000 h workflash (64kb ) (64kb) (64kb) 0034 0000 h 0034 0000 h 0034 0000 h reserved reserved reserved 8000 0000 h 8000 0000 h 8000 0000 h external area external area external area ffff fff f h ffff fff f h fff f h reserved reserved reserved reserved reserved r eserved ffff 003 9 0000 h 003 9 2 000 h 003 9 0000 h 003 9 2 000 h interrupt vector reset vector 000 f fc 00 h 0010 0000 h interrupt vector reset vector 000 f fc 00 h 0010 0000 h interrupt vector reset vector 000 f fc 00 h reserved reserved reserved reserved reserved d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 51 confidential ? mb91f525, mb91f526 mb91f525 mb91f52 6 0000 000 0 h i/o 0000 0000 h i/o 0000 4000 h backup ram (8kb) 0000 4000 h backup ram (8kb) 0000 6000 h i/o 0000 6000 h i/o 0001 0000 h ram (96kb) 0001 0000 h ram (128kb) 0002 8000 h 0003 0000 h reserved reserved 0007 0000 h 0007 0000 h fla sh memory flash memory (768+64)kb (1024+64)kb 0014 0000 h 0018 0000 h reserved reserved 0033 0000 h workflash 0033 0000 h workflash (64kb) (64kb) 0034 0000 h 0034 0000 h reserved reserved 8000 0000 h 8000 0000 h external area external area ffff ffff h ffff fff f h 003 9 0000 h 003 9 2 000 h 003 9 0000 h 003 9 2 000 h interrupt vector flash memory reset vector 000 f fc 00 h 00 1 0 00 00 h flash memory interrupt vector reset vector 000 f fc 00 h 00 1 0 00 00 h reserved d a t a s h e e t 52 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? i/o map the following i/o map shows the relationship between memory space and registers for peripheral resources. legend of i/o map read/write attribute (r: read w: write) address address offset value/ regi ster name block + 0 +1 +2 +3 000090 h bt1tmr[r] h 0000000000000000 bt1tmcr[r/w]b,h,w 00000000 00000000 base timer 1 0000 94 h - bt1stc[r/w] b 00000000 - - 000098 h bt1pcsr/bt1prll[r /w] h 0000000000000000 bt1pdu t/bt1prlh/bt1dtbf[r/w] h 000000000000 0000 00009c h btsel[r/w] b ---- 000 0 - btsssr[w] b,h -------- ------ 11 0000a0 h aderh [r/w]b, h, w 00000000 00000000 aderl [r/w]b, h, w 00000000 00000000 a/d converter 0000a4 h adcs1 [r/w] b, h,w 00000000 adcs0 [r/w] b, h,w 00000000 adcr1 [r] b, h ,w ------ xx adcr0 [r] b, h,w xxxxx xxx 0000a8 h adct1 [r/w] b, h,w 00010000 adct0 [r/w] b, h,w 00101100 adsch [r/w] b, h,w --- 00000 adech [r/w] b, h,w --- 00000 data access attribute b: byte h: half - word w: word (note)the access by the data access attribute not described is disabled. initial register value after reset the initial register value after reset indicates as follows: "1": initial value "1" "0": initial value "0" "x": initial value undefined " - ": reserved bit/undefined bit "*": initia l value "0" or "1" accor d ing to the setting note: the access to addresses not described is disabled. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 53 confidential address address offset value / register name block +0 +1 +2 +3 000000 h pdr00 [r/w] b,h,w xxxxxxxx pdr01 [r/w] b,h,w xxxxxxxx pdr02 [r/w] b,h,w xxxxx xxx pdr03 [r/w] b,h,w xxxxxxxx port data register 000004 h pdr04 [r/w] b,h,w xxxxxxxx pdr05 [r/w] b,h,w xxxxxxxx pdr06 [r/w] b,h,w xxxxxxxx pdr07 [r/w] b,h,w xxxxxxxx 000008 h pdr08 [r/w] b,h,w xxxxxxxx pdr09 [r/w] b,h,w xxxxxxxx pdr10 [r/w] b,h,w xxxxxxx x pdr11 [r/w] b,h,w xxxxxxxx 00000c h pdr12 [r/w] b,h,w xxxxxxxx pdr13 [r/w] b,h,w - xxxxxxx pdr14 [r/w] b,h,w --- xxx -- pdr15 [r/w] b,h,w -- xxxxxx 000010 h D D D D 000014 h D D D D 000018 h pdr16 [r/w] b,h,w xxxxxxxx pdr17 [r/w] b,h,w xxxxxxxx pdr18 [r/w] b,h,w xxxxxxxx pdr19 [r/w] b,h,w xxxxxxxx 00001c h to 000034 h D D D D reserved 000038 h wdtecr0 [r/w] b,h,w --- 00000 D D D watchdog timer [s] 00003c h wd tcr0 [r/w] b,h,w - 0 -- 0000 wdtcpr0 [w] b,h,w 00000000 wdtcr1 [r] b,h,w ---- 0110 wdtcpr1 [w] b,h,w 00000000 000040 h D D D D reserved 000044 h dicr [r/w] b ,h,w ------- 0 D D D delayed interrupt 000048 h to 00005c h D D D D reserved 000060 h tmrlra0 [r/w ] h xxxxxxxx xxxxxxxx tmr0 [r] h xxxxxxxx xxxxxxxx reload timer 0 000064 h tmrlrb0 [r/w] h xxxxxxxx xxxxxxxx tmcsr0 [r/w] b,h,w 00000000 0 - 000000 000068 h tmrlra7 [r/w] h xxxxxxxx xxxxxxxx tmr7 [r] h xxxxxxxx xxxxxxxx reload timer 7 00006c h tmrlrb7 [r/w] h xxxxxxxx xxxxxxxx tmcsr7 [r/w] b,h,w 00000000 0 - 000000 000070 h D frs8 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 free - run timer selection register 8 000074 h D frs9 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 free - run timer selection register 9 000078 h D D D ocls67 [r/w] b,h,w ---- 0000 ocu67 output level control register d a t a s h e e t 54 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 00007c h D D D ocls89 [r/w] b,h,w ---- 0000 ocu89 output level control register 000080 h bt0tmr [r] h 00000000 00000000 bt0tmcr [r/w] h - 000 -- 00 - 000 - 000 base timer 0 000084 h bt0tmcr2 [r/w] b ------- 0 bt0stc [r/w] b - 0 - 0 - 0 - 0 D D 000088 h bt0pcsr/bt0 prll [r/w] h 00000000 00000000 bt0pdut/bt0prlh/bt0dtbf [r/w] h 00000000 00000000 00008c h D D D D reserved 000090 h bt1tmr [r] h 00000000 00000000 bt1tmcr [r/w] h - 000 -- 00 - 000 - 000 base timer 1 000094 h bt1tmcr2 [r/w] b ------- 0 bt1stc [r/w] b - 0 - 0 - 0 - 0 D D 000098 h bt1pcsr/bt1prll [r/w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf [r/w] h 00000000 00000000 00009c h btsel01 [r/w] b ---- 0000 D btsssr [w] b,h -------- ------ 11 base timer 0,1 0000a0 h to 0000fc h D D D D reserved 000100 h tmrlra1 [r/w] h xxxx xxxx xxxxxxxx tmr1 [r] h xxxxxxxx xxxxxxxx reload timer 1 000104 h tmrlrb1 [r/w] h xxxxxxxx xxxxxxxx tmcsr1 [r/w] b, h,w 00000000 0 - 000000 000108 h tmrlra2 [r/w] h xxxxxxxx xxxxxxxx tmr2 [r] h xxxxxxxx xxxxxxxx reload timer 2 00010c h tmrlrb2 [r/w] h xxxx xxxx xxxxxxxx tmcsr2 [r/w] b,h,w 00000000 0 - 000000 000110 h tmrlra3 [r/w] h xxxxxxxx xxxxxxxx tmr3 [r] h xxxxxxxx xxxxxxxx reload timer 3 000114 h tmrlrb3 [r/w] h xxxxxxxx xxxxxxxx tmcsr3 [r/w] b,h,w 00000000 0 - 000000 000118 h mscy4 [r] h,w xxxxxxxx xxxx xxxx xxxxxxxx xxxxxxxx input capture 4,5 cycle measurement data register 45 00011c h mscy5 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000120 h occp6 [r/w] w 00000000 00000000 00000000 00000000 output compare 6,7 32 - bit ocu 000124 h occp7 [r/w] w 00000000 00000000 00000000 00000000 000128 h D D ocsh67 [r/w] b,h,w --- 0 -- 00 ocsl67 [r/w] b,h,w 0000 -- 00 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 55 confidential address address offset value / register name block +0 +1 +2 +3 00012c h occp8 [r/w] w 00000000 00000000 00000000 00000000 output compare 8,9 32 - bit ocu 000130 h occp9 [r/w] w 00000000 00000000 00000000 00000000 000134 h D D ocsh89 [r/w] b,h,w --- 0 - - 00 ocsl89 [r/w] b,h,w 0000 -- 00 000138 h to 0001b4 h D D D D reserved 0001b8 h epfr64 [r/w] b,h,w ----- 00 - epfr65 [r/w] b,h,w 0000 - 000 epfr66 [r/w] b,h,w -- 000000 epfr67 [r/w] b,h,w ---- 0000 extended port function register 0001bc h epfr68 [r/w] b,h,w ---- 0000 epfr69 [r/w] b,h,w ---- 0000 epfr70 [r/w] b,h,w --- 00000 epfr71 [r/w] b,h,w - 0 - 0 - 0 - 0 0001c0 h epfr72 [r/w] b,h,w 000000 - 0 epfr73 [r/w] b,h,w 00000000 epfr74 [r/w] b,h,w 00000000 epfr75 [r/w] b,h,w 00000000 0001c4 h epfr76 [r/w] b,h,w 0000 0000 epfr77 [r/w] b,h,w -- 000000 epfr78 [r/w] b,h,w ------ 00 epfr79 [r/w] b,h,w 00000000 0001c8 h epfr80 [r/w] b,h,w --- 00000 epfr81 [r/w] b,h,w 00000000 epfr82 [r/w] b,h,w 00000000 epfr83 [r/w] b,h,w - 0000000 0001cc h epfr84 [r/w] b,h,w 00000000 epfr85 [r/w] b,h,w -- 000000 epfr86 [r/w] b,h,w --- 00000 epfr87 [r/w] b,h,w ------ 00 0001d0 h epfr88 [r/w] b,h,w ------- 0 D D D 0001d4 h D D D D reserved 0001d8 h tmrlra4 [r/w] h xxxxxxxx xxxxxxxx tmr4 [r] h xxxxxxxx xxxxxxxx reload timer 4 0001dc h tmrlrb4 [r/w] h xxxxxxxx xxxxxxxx tmcsr4 [r/w] b, h,w 00000000 0 - 000000 0001 e0 h to 0001 ec h D D D D reserved 0001f0 h tmrlra5 [r/w] h xxxxxxxx xxxxxxxx tmr5 [r] h xxxxxxxx xxxxxxxx reload timer 5 0001f4 h tmrlrb5 [r/w] h xxxxxxxx xxxxxxxx tmcsr5 [r/w] b, h,w 00000000 0 - 000000 0001f8 h tmrlra6 [r/w] h xxxxxxxx xxxxxxxx tmr6 [r] h xxxxxxxx xxxxxxxx reload timer 6 0001fc h tmrlrb6 [r/w] h xxxxxxxx xxxxxxxx tmcsr6 [r/w] b, h,w 00000000 0 - 000000 000200 h to 000238 h D D D D reserved 00023c h dacr0 [r/w] b,h,w ------- 0 dadr0 [r/w] b,h,w xxxxxxxx dacr1 [r/w] b,h,w ------- 0 dadr1 [r/w] b,h,w xxxxxxxx da converter d a t a s h e e t 56 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000240 h cpclr3 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 3 32 - bit frt 000244 h tcdt3 [r/w] w 00000000 00000000 00000000 00000000 000248 h tccsh3 [r/w] b,h,w 0 ----- 00 tccsl3 [r/w] b,h,w - 1 - 00000 D D 00024c h cpclr4 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 4 32 - bit frt 000250 h tcdt4 [r/w] w 00000000 00000000 00000000 00000000 000254 h tccsh4 [r/w] b,h,w 0 ----- 00 tccsl4 [r/w] b,h,w - 1 - 00000 D D 000258 h to 0002c0 h D D D D res erved 0002c4 h to 0002fc h D D D D reserved 000300 h to 00030c h D D D D reserved 000310 h D D mpucr [r/w] h 000000 - 0 ---- 0100 mpu [s] (only cpu core can access this area) 000314 h D D D D 000318 h D 00031c h D D D 000320 h dpvar [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000324 h D D dpvsr [r/w] h -------- 00000 -- 0 000328 h dear [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00032c h D D desr [r/w] h -------- 00000 -- 0 000330 h pabr0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000334 h D D pacr0 [r/w] h 00 0000 - 0 00000 -- 0 000338 h pabr1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00033c h D D pacr1 [r/w] h 000000 - 0 00000 -- 0 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 57 confidential address address offset value / register name block +0 +1 +2 +3 000340 h pabr2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 mpu [s] (only cpu core can access this area) 000344 h D D pacr2 [r/w ] h 000000 - 0 00000 -- 0 000348 h pabr3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00034c h D D pacr3 [r/w] h 000000 - 0 00000 -- 0 000350 h pabr4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000354 h D D pacr4 [r/w] h 000000 - 0 00000 -- 0 000358 h pabr5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00035c h D D pacr5 [r/w] h 000000 - 0 00000 -- 0 000360 h pabr6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000364 h D D pacr6 [r/w] h 000000 - 0 00000 -- 0 000368 h pabr7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 0003 6c h D D pacr7 [r/w] h 000000 - 0 00000 -- 0 000370 h to 0003ac h D reserved [s] 0003b0 h to 0003fc h D D D D reserved [s] 000400 h icsel0 [r/w] b,h,w ----- 000 icsel1 [r/w] b,h,w ----- 000 icsel2 [r/w] b,h,w ------- 0 icsel3 [r/w] b,h,w ------- 0 dma request gener ation and clear 000404 h D icsel5 [r/w] b,h,w ----- 000 icsel6 [r/w] b,h,w ---- 0000 icsel7 [r/w] b,h,w ---- 0000 000408 h icsel8 [r/w] b,h,w ------ 00 icsel9 [r/w] b,h,w ------ 00 icsel10 [r/w] b,h,w ------ 00 icsel11 [r/w] b,h,w ----- 000 00040c h D icsel13 [ r/w] b,h,w ------ 00 icsel14 [r/w] b,h,w ------ 00 icsel15 [r/w] b,h,w ------ 00 000410 h icsel16 [r/w] b,h,w ---- 0000 icsel17 [r/w] b,h,w ------ 00 icsel18 [r/w] b,h,w --- 00000 icsel19 [r/w] b,h,w ----- 000 000414 h icsel20 [r/w] b,h,w ----- 000 icsel21 [r/w] b,h,w ------ 00 icsel22 [r/w] b,h,w ------ 00 icsel23 [r/w] b,h,w ------ 00 d a t a s h e e t 58 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000418 h irpr0h [r] b,h,w 00 ------ irpr0l [r] b,h,w 00 ------ irpr1h [r] b,h,w 00 ------ irpr1l [r] b,h,w 00 ------ interrupt request batch reading register 00041c h D D irpr3h [r] b,h,w 000000 -- irpr3l [r] b,h,w 000000 -- 000420 h irpr4h [r] b,h,w 0000 ---- irpr4l [r] b,h,w 0000 ---- irpr5h [r] b,h,w 0000 ---- irpr5l [r] b,h,w 000 ----- 000424 h irpr6h [r] b,h,w -- 00 ---- irpr6l [r] b,h,w 0000 ---- irpr7h [r] b,h,w - 0 - 00 -- - irpr7l [r] b,h,w ------ 00 000428 h irpr8h [r] b,h,w -- 0 ----- irpr8l [r] b,h,w - 00 ----- irpr9h [r] b,h,w - 0 ------ irpr9l [r] b,h,w - 0 ------ 00042c h irpr10h [r] b,h,w - 0 ------ irpr10l [r] b,h,w - 0 ------ irpr11h [r] b,h,w 0 ------- irpr11l [r] b,h,w 0 ---- --- 000430 h irpr12h [r] b,h,w -- 0000 -- irpr12l [r] b,h,w ---- 00 -- irpr13h [r] b,h,w 00 ------ irpr13l [r] b,h,w 00 ------ 000434 h irpr14h [r] b,h,w 00000000 irpr14l [r] b,h,w 00000000 irpr15h [r] b,h,w 000 ----- irpr15l [r] b,h,w 0000000 - 000438 h icsel2 4 [r/w] b,h,w ------ 00 icsel25 [r/w] b,h,w --- 00000 icsel26 [r/w] b,h,w ------- 0 icsel27 [r/w] b,h,w ------- 0 dma request generation and clear 00043c h D D D D reserved [s] 000440 h icr00 [r/w] b,h,w --- 11111 icr01 [r/w] b,h,w --- 11111 icr02 [r/w] b,h,w -- - 11111 icr03 [r/w] b,h,w --- 11111 interrupt controller [s] 000444 h icr04 [r/w] b,h,w --- 11111 icr05 [r/w] b,h,w --- 11111 icr06 [r/w] b,h,w --- 11111 icr07 [r/w] b,h,w --- 11111 000448 h icr08 [r/w] b,h,w --- 11111 icr09 [r/w] b,h,w --- 11111 icr10 [r/w] b,h, w --- 11111 icr11 [r/w] b,h,w --- 11111 00044c h icr12 [r/w] b,h,w --- 11111 icr13 [r/w] b,h,w --- 11111 icr14 [r/w] b,h,w --- 11111 icr15 [r/w] b,h,w --- 11111 000450 h icr16 [r/w] b,h,w --- 11111 icr17 [r/w] b,h,w --- 11111 icr18 [r/w] b,h,w --- 11111 icr19 [r/ w] b,h,w --- 11111 000454 h icr20 [r/w] b,h,w --- 11111 icr21 [r/w] b,h,w --- 11111 icr22 [r/w] b,h,w --- 11111 icr23 [r/w] b,h,w --- 11111 000458 h icr24 [r/w] b,h,w --- 11111 icr25 [r/w] b,h,w --- 11111 icr26 [r/w] b,h,w --- 11111 icr27 [r/w] b,h,w --- 11111 00045c h icr28 [r/w] b,h,w --- 11111 icr29 [r/w] b,h,w --- 11111 icr30 [r/w] b,h,w --- 11111 icr31 [r/w] b,h,w --- 11111 000460 h icr32 [r/w] b,h,w --- 11111 icr33 [r/w] b,h,w --- 11111 icr34 [r/w] b,h,w --- 11111 icr35 [r/w] b,h,w --- 11111 000464 h icr36 [r/w] b,h,w --- 11111 icr37 [r/w] b,h,w --- 11111 icr38 [r/w] b,h,w --- 11111 icr39 [r/w] b,h,w --- 11111 000468 h icr40 [r/w] b,h,w --- 11111 icr41 [r/w] b,h,w --- 11111 icr42 [r/w] b,h,w --- 11111 icr43 [r/w] b,h,w --- 11111 00046c h icr44 [r/w] b,h,w --- 11111 icr45 [r/w] b,h,w --- 11111 icr46 [r/w] b,h,w --- 11111 icr47 [r/w] b,h,w --- 11111 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 59 confidential address address offset value / register name block +0 +1 +2 +3 000470 h to 00047c h D D D D reserved [s] 000480 h rstrr [r] b,h,w xxxx -- xx rstcr [r/w] b,h,w 111 ---- 0 stbcr [r/w] b,h,w * 000 --- 11 D reset control [s] power control [s] * : writing stbcr by dma is forbidden 000484 h D D D D reserved [s] 000488 h divr0 [r/w] b,h,w 000 ----- d ivr1 [r/w] b,h,w 0001 ---- divr2 [r/w] b,h,w 0011 ---- D clock control [s] 00048c h D D D D reserved [s] 000490 h iorr0 [r/w] b,h,w - 0000000 iorr1 [r/w] b,h,w - 0000000 iorr2 [r/w] b,h,w - 0000000 iorr3 [r/w] b,h,w - 0000000 dma request by peripheral [s] 00049 4 h iorr4 [r/w] b,h,w - 0000000 iorr5 [r/w] b,h,w - 0000000 iorr6 [r/w] b,h,w - 0000000 iorr7 [r/w] b,h,w - 0000000 000498 h iorr8 [r/w] b,h,w - 0000000 iorr9 [r/w] b,h,w - 0000000 iorr10 [r/w] b,h,w - 0000000 iorr11 [r/w] b,h,w - 0000000 00049c h iorr12 [r/w] b, h,w - 0000000 iorr13 [r/w] b,h,w - 0000000 iorr14 [r/w] b,h,w - 0000000 iorr15 [r/w] b,h,w - 0000000 0004a0 h D D D D reserved 0004a4 h canpre [r/w] b,h,w --- 00000 D D D can prescaler 0004a8 h D D cscfg[r/w]b,h,w --- 0 ---- cmcfg[r/w]b,h,w 00000000 clock monitor control register 0004ac h aderh0[r/w] b,h 11111111 11111111 aderl0[r/w] b,h 11111111 11111111 a nalog inp ut control register 0 0004b0 h D aderl1[r/w] b,h 11111111 11111111 a nalog input control register 1 0004b4 h D D D D reserved 0004b8 h cucr0 [r/w] b,h,w -------- --- 0 -- 00 cutd0 [r/w] b,h,w 10000000 00000000 rtc/wdt1 calibration 0004bc h cutr0 [r] b,h,w ---- ---- 00000000 00000000 00000000 0004c0 h D D D D 0004c4 h cucr1 [r/w] b,h,w -------- --- 0 -- 00 cutd1 [r/w] b,h,w 11000011 01010000 0004c8 h cutr1 [r] b,h,w -------- 00000000 00000000 00000000 0004cc h to 00050c h D D D D reserved d a t a s h e e t 60 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000510 h cselr [r/w] b,h,w 001 --- 00 cmonr [r] b,h,w 001 --- 00 mtmcr [r/w] b,h,w 00001111 stmcr [r/w] b,h,w 0000 - 111 clock control [s] 000514 h pllcr [r/w] b,h,w -------- 11110000 cstbr [r/w] b,h,w - 0000000 ptmcr [r/w] b,h,w 00 ------ 000518 h D D cpuar [r/w] b,h,w 0 ---- x xx D reset control [s] 00051c h D D D D reserved [s] 000520 h ccpsselr [r/w] b,h,w ------- 0 D D ccpsdivr [r/w] b,h,w - 000 - 000 clock control 2 [s] 000524 h D ccpllfbr [r/w] b,h,w - 0000000 ccssfbr0 [r/w] b,h,w -- 000000 ccssfbr1 [r/w] b,h,w --- 00000 00 0528 h D ccssccr0 [r/w] b,h,w ---- 0000 ccssccr1 [r/w] h,w 000 ----- -------- 00052c h D cccgrcr0 [r/w] b,h,w 00 ---- 00 cccgrcr1 [r/w] b,h,w 00000000 cccgrcr2 [r/w] b,h,w 00000000 000530 h ccrtselr [r/w] b,h,w 0 ------ 0 D ccpmucr0 [r/w] b,h,w 0 ----- 00 c cpmucr1 [r/w] b,h,w 0 -- 00000 000534 h to 00054c h D D D D reserved 000550 h eirr0 [r/w] b,h,w xxxxxxxx enir0 [r/w] b,h,w 00000000 elvr0 [r/w] b,h,w 00000000 00000000 external interrupt (int0 to 7) 000554 h eirr1 [r/w] b,h,w xxxxxxxx enir1 [r/w] b,h,w 0000 0000 elvr1 [r/w] b,h,w 00000000 00000000 external interrupt (int8 to 15) 000558 h D D D D reserved 00055c h D D wtdr [r/w] h 00000000 00000000 real time clock (rtc) 000560 h D wtcrh [r/w] b ------ 00 wtcrm [r/w] b,h 00000000 wtcrl [r/w] b,h ---- 00 - 0 00056 4 h D wtbrh [r/w] b -- xxxxxx wtbrm [r/w] b xxxxxxxx wtbrl [r/w] b xxxxxxxx 000568 h wthr [r/w] b,h --- 00000 wtmr [r/w] b,h -- 000000 wtsr [r/w] b -- 000000 D 00056c h D csvcr [r/w] b 000111 -- D D clock supervisor 000570 h to 00057c h D D D D reserved d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 61 confidential address address offset value / register name block +0 +1 +2 +3 000580 h regsel [r/w] b,h,w 0110011 - D D D regulator control / low voltage detection 000584 h lvd5r [r/w] b,h,w ------- 1 lvd5f [r/w] b,h,w 00000001 lvd [r/w] b,h,w 01000 -- 0 D 000588 h to 00058c h D D D D reserved 000590 h pmustr [r/w] b,h,w 0 ----- 1x pmuctlr [r/w] b,h,w 0 - 00 ---- pwrtmctl [r/w] b,h,w ----- 011 D pmu 000594 h pmuintf0 [r/w] b,h,w 00000000 pmuintf1 [r/w] b,h,w 00000000 pmuintf2 [r/w] b,h,w 0000 ---- D 000598 h D D D D 00059c h to 0005bc h D D D D reserved 0005c0 h to 0005fc h D D D D reserved 000600 h asr0 [r/w] w 00000000 00000000 -------- 1111 - 001 external bus interface [s] 000604 h asr1 [r/w] w xxxxxxxx xxxxxxxx -------- xxxx - xx0 000608 h asr2 [r/w] w xxxxxxxx xxxxxxxx -------- xxxx - xx0 00060c h asr3 [r/w] w xxxxxxxx xxxxxxxx - ------- xxxx - xx0 000610 h to 00063c h D D D D reserved [s] 000640 h acr0 [r/w] w -------- -------- -------- 01 -- 00 -- external bus interface [s] 000644 h acr1 [r/w] w -------- -------- -------- xx -- xx -- 000648 h acr2 [r/w] w -------- -------- -------- xx -- xx -- 00064c h acr3 [r/w] w -------- -------- -------- xx -- xx -- 000650 h to 00067c h D D D D reserved [s] 000680 h awr0 [r/w] w ---- 1111 00000000 11110000 00000 - 0 - external bus interface [s] 000684 h awr1 [r/w] w ---- xxxx xxxxxxxx xxxxxxxx xxxxx - x - d a t a s h e e t 62 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 00068 8 h awr2 [r/w] w ---- xxxx xxxxxxxx xxxxxxxx xxxxx - x - external bus interface [s] 00068c h awr3 [r/w] w ---- xxxx xxxxxxxx xxxxxxxx xxxxx - x - 000690 h to 0006fc h D D D D reserved [s] 000700 h to 00070c h D D D D reserved 000710 h bpccra [r/w] b 00000000 bpccrb [r/w] b 00000000 bpccrc [r/w] b 00000000 D bus performance counter 000714 h bpctra [r/w] w 00000000 00000000 00000000 00000000 000718 h bpctrb [r/w] w 00000000 00000000 00000000 00000000 00071c h bpctrc [r/w] w 00000000 00000000 00000000 00000000 00072 0 h to 0007f8 h D D D D reserved 0007fc h bmodr [r] b, h, w xxxxxxxx D D D mode register 000800 h to 00083c h D D D D reserved [s] 000840 h fctlr [r/w] h - 0 -- 1000 0 -- 0 ---- D fstr [r/w] b ----- 001 flash memory register [s] 000844 h to 000854 h D D D D reserved [s] 000858 h D D wren [r/w] h 00000000 00000000 wild register [s] 00085c h to 00087c h D D D D reserved [s] 000880 h wrar00 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 000884 h wrdr00 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000888 h w rar01 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00088c h wrdr01 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000890 h wrar02 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 000894 h wrdr02 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 63 confidential address address offset value / register name block +0 +1 +2 +3 000898 h wrar03 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 00089c h wrdr03 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a0 h wrar04 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008a4 h wrdr04 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a8 h wrar05 [ r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ac h wrdr05 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b0 h wrar06 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008b4 h wrdr06 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b8 h wrar07 [r/w] w ----- --- -- xxxxxx xxxxxxxx xxxxxx -- 0008bc h wrdr07 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c0 h wrar08 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008c4 h wrdr08 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c8 h wrar09 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008cc h wrdr09 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d0 h wrar10 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008d4 h wrdr10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d8 h wrar11 [r/w] w -------- -- xxxxxx xxxxxxxx xx xxxx -- 0008dc h wrdr11 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e0 h wrar12 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008e4 h wrdr12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e8 h wrar13 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 000 8ec h wrdr13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f0 h wrar14 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- d a t a s h e e t 64 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0008f4 h wrdr14 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx wild register [s] 0008f8 h wrar15 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008fc h wrdr15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000900 h tpuunlock [r/w] w 00000000 00000000 00000000 00000000 time protection unit [s] 000904 h tpulst [r] b,h,w ------- 0 D tpuvst [r/w] b,h,w ----- 000 D 000908 h tpucfg [r/w] b,h,w ------- 0 0 - 000000 -------- ------- 0 00090c h tputir [r] b,h,w 00000000 D D D 000910 h tputst [r] b,h,w 00000000 D D D 000914 h tputie [r/w] b,h,w 00000000 D D D 000918 h tputmid [r] b,h,w 000 00000 00000000 00000000 00000000 00091c h to 00092c h D D D D 000930 h tputcn00 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000934 h tputcn01 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000938 h tputcn02 [r/w] b,h,w 000000 -- 00000000 00000000 0 0000000 00093c h tputcn03 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000940 h tputcn04 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000944 h tputcn05 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000948 h tputcn06 [r/w] b,h,w 000000 -- 0000000 0 00000000 00000000 00094c h tputcn07 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000950 h tputcn10 [r/w] b,h,w --- 00000 D D D 000954 h tputcn11 [r/w] b,h,w --- 00000 D D D 000958 h tputcn12 [r/w] b,h,w --- 00000 D D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 65 confidential address address offset value / register name block +0 +1 +2 +3 00095c h tputcn13 [r/w] b,h,w --- 00000 D D D time protection unit [s] 000960 h tputcn14 [r/w] b,h,w --- 00000 D D D 000964 h tputcn15 [r/w] b,h,w --- 000 00 D D D 000968 h tputcn16 [r/w] b,h,w --- 00000 D D D 00096c h tputcn17 [r/w] b,h,w --- 00000 D D D 000970 h tputcc0 [r] b,h,w -------- 00000000 00000000 00000000 000974 h tputcc1 [r] b,h,w -------- 00000000 00000000 00000000 000978 h tputcc2 [r] b,h ,w -------- 00000000 00000000 00000000 00097c h tputcc3 [r] b,h,w -------- 00000000 00000000 00000000 000980 h tputcc4 [r] b,h,w -------- 00000000 00000000 00000000 000984 h tputcc5 [r] b,h,w -------- 00000000 00000000 00000000 000988 h tputcc6 [r] b,h ,w -------- 00000000 00000000 00000000 00098c h tputcc7 [r] b,h,w -------- 00000000 00000000 00000000 000990 h to 0009fc h D D D D 000a00 h to 000bec h D D D D reserved 000bf0 h hscfr [r/w] b,h,w -------- ------ 00 00000000 00000000 ocdu 000bf4 h D D D D 000bf8 h D D mbr [r/w] b,h,w 00 ------ xxxxxxxx 000bfc h D D uer [w] b,h,w -------- ------- x 000c00 h dccr0 [r/w] w 0 ---- 0 00 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000c04 h dcsr0 [r/w] h 0 ------- ----- 000 dtcr0 [r/w] h 00000000 00000000 d a t a s h e e t 66 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000c08 h dsar0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dma controller [s] 000c0c h ddar0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxx xxx 000c10 h dccr1 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c14 h dcsr1 [r/w] h 0 ------- ----- 000 dtcr1 [r/w] h 00000000 00000000 000c18 h dsar1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c1c h ddar1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx x 000c20 h dccr2 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c24 h dcsr2 [r/w] h 0 ------- ----- 000 dtcr2 [r/w] h 00000000 00000000 000c28 h dsar2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c2c h ddar2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c30 h dccr3 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c34 h dcsr3 [r/w] h 0 ------- ----- 000 dtcr3 [r/w] h 00000000 00000000 000c38 h dsar3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c3c h ddar3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c40 h dccr4 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c44 h dcsr4 [r/w] h 0 ------- ----- 000 dtcr4 [r/w] h 00000000 00000000 000c48 h dsar4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c4c h ddar4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0 00c50 h dccr5 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c54 h dcsr5 [r/w] h 0 ------- ----- 000 dtcr5 [r/w] h 00000000 00000000 000c58 h dsar5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c5c h ddar5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000 c60 h dccr6 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c64 h dcsr6 [r/w] h 0 ------- ----- 000 dtcr6 [r/w] h 00000000 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 67 confidential address address offset value / register name block +0 +1 +2 +3 000c68 h dsar6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dma controller [s] 000c6c h ddar6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxx x xxxxxxxx 000c70 h dccr7 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c74 h dcsr7 [r/w] h 0 ------- ----- 000 dtcr7 [r/w] h 00000000 00000000 000c78 h dsar7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c7c h ddar7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c80 h dccr8 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c84 h dcsr8 [r/w] h 0 ------- ----- 000 dtcr8 [r/w] h 00000000 00000000 000c88 h dsar8 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c8c h ddar8 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx x xxxxxxx 000c90 h dccr9 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c94 h dcsr9 [r/w] h 0 ------- ----- 000 dtcr9 [r/w] h 00000000 00000000 000c98 h dsar9 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c9c h ddar9 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxx xxxxx 000ca0 h dccr10 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000ca4 h dcsr10 [r/w] h 0 ------- ----- 000 dtcr10 [r/w] h 00000000 00000000 000ca8 h dsar10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cac h ddar10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cb0 h dccr11 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cb4 h dcsr11 [r/w] h 0 ------- ----- 000 dtcr11 [r/w] h 00000000 00000000 000cb8 h dsar11 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cbc h ddar11 [r/w] w xxxxxxxx xxxxxxxx xxxx xxxx xxxxxxxx d a t a s h e e t 68 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000cc0 h dccr12 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000cc4 h dcsr12 [r/w] h 0 ------- ----- 000 dtcr12 [r/w] h 00000000 00000000 000cc8 h dsar12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ccc h ddar12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cd0 h dccr13 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cd4 h dcsr13 [r/w] h 0 ------- ----- 000 dtcr13 [r/w] h 00000000 00000000 000cd8 h dsar13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cdc h ddar13 [r/w ] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ce0 h dccr14 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000ce4 h dcsr14 [r/w] h 0 ------- ----- 000 dtcr14 [r/w] h 00000000 00000000 000ce8 h dsar14 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cec h ddar14 [ r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cf0 h dccr15 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cf4 h dcsr15 [r/w] h 0 ------- ----- 000 dtcr15 [r/w] h 00000000 00000000 000cf8 h dsar15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cfc h ddar1 5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000d00 h to 000df0 h D D D D reserved [s] 000df4 h D D dnmir [r/w] b 0 ------ 0 dilvr [r/w] b --- 11111 dma controller [s] 000df8 h dmacr[r/w] w 0 ------- -------- 0 ------- -------- 000dfc h D D D D reserved [s] 000e00 h ddr00 [r/w] b,h,w 00000000 ddr01 [r/w] b,h,w 00000000 ddr02 [r/w] b,h,w 00000000 ddr03 [r/w] b,h,w 00000000 data direction register 000e04 h ddr04 [r/w] b,h,w 00000000 ddr05 [r/w] b,h,w 00000000 ddr06 [r/w] b,h,w 00000000 ddr07 [r/w] b,h,w 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 69 confidential address address offset value / register name block +0 +1 +2 +3 000e08 h ddr08 [r/w] b,h,w 00000000 ddr09 [r/w] b,h,w 00000000 ddr10 [r/w] b,h,w 00000000 ddr11 [r/w] b,h,w 00000000 data direction register 000e0c h ddr12 [r/w] b,h,w 00000000 ddr13 [r/w] b,h,w - 0000000 ddr14 [r/w] b,h,w --- 000 -- ddr15 [r/w] b,h,w -- 000 000 000e10 h D D D D 000e14 h D D D D 000e18 h ddr16 [r/w] b,h,w 00000000 ddr17 [r/w] b,h,w 00000000 ddr18 [r/w] b,h,w 00000000 ddr19 [r/w] b,h,w 00000000 000e1c h D D D D reserved 000e20 h pfr00 [r/w] b,h,w 00000000 pfr01 [r/w] b,h,w 00000000 pfr02 [r /w] b,h,w 00000000 pfr03 [r/w] b,h,w 00000000 port function register 000e24 h pfr04 [r/w] b,h,w 00000000 pfr05 [r/w] b,h,w 00000000 pfr06 [r/w] b,h,w 00000000 pfr07 [r/w] b,h,w 00000000 000e28 h pfr08 [r/w] b,h,w 00000000 pfr09 [r/w] b,h,w 00000000 pfr10 [r/w] b,h,w 00000000 pfr11 [r/w] b,h,w 00000000 000e2c h pfr12 [r/w] b,h,w 00000000 pfr13 [r/w] b,h,w - 0000000 pfr14 [r/w] b,h,w --- 000 -- pfr15 [r/w] b,h,w -- 000000 000e30 h D D D D 000e34 h D D D D 000e38 h pfr16 [r/w] b,h,w 00000000 pfr17 [r/w] b,h,w 00000000 pfr18 [r/w] b,h,w 00000000 pfr19 [r/w] b,h,w 00000000 000e3c h D D D D reserved 000e40 h pddr00 [r] b,h,w xxxxxxxx pddr01 [r] b,h,w xxxxxxxx pddr02 [r] b,h,w xxxxxxx x pddr03 [r] b,h,w xxxxxxxx port direct read register 000e44 h pddr04 [r] b,h,w xxxxxxxx pddr05 [r] b,h,w xxxxxxxx pddr06 [r] b,h,w xxxxxxxx pddr07 [r] b,h,w xxxxxxxx 000e48 h pddr08 [r] b,h,w xxxxxxxx pddr09 [r] b,h,w xxxxxxxx pddr10 [r] b,h,w xxxxxxxx p ddr11 [r] b,h,w xxxxxxxx 000e4c h pddr12 [r] b,h,w xxxxxxxx pddr13 [r] b,h,w - xxxxxxx pddr14 [r] b,h,w --- xxx -- pddr15 [r] b,h,w -- xxxxxx 000e50 h D D D D 000e54 h D D D D 000e58 h pddr16 [r] b,h,w xxxxxxxx pddr17 [r] b,h,w xxxxxxxx pddr18 [r] b,h,w xxxxxxxx pddr19 [r] b,h,w xxxxxxxx 000e5c h D D D D reserved 000e60 h epfr00 [r/w] b,h,w 00000000 epfr01 [r/w] b,h,w - 0 - 0 - 000 epfr02 [r/w] b,h,w -- -- 0000 epfr03 [r/w] b,h,w --- 000 - 0 extended port function register 000e64 h epfr04 [r/w] b,h,w ---- 00 - 0 epfr05 [r/w] b,h,w ---- 0000 epfr06 [r/w] b,h,w ---- 000 - epfr07 [r/w] b,h,w --- 00000 d a t a s h e e t 70 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000e68 h epfr08 [r/w] b,h,w --- 00000 epfr09 [r/w] b,h ,w ----- 00 - epfr10 [r/w] b,h,w ---- 0000 epfr11 [r/w] b,h,w ---- 0000 extended port function register 000e6c h epfr12 [r/w] b,h,w ---- 0000 epfr13 [r/w] b,h,w ------ 00 epfr14 [r/w] b,h,w ------ 00 epfr15 [r/w] b,h,w ----- 000 000e70 h D D D D 000e74 h D D D D 000e78 h D D epfr26 [r/w] b,h,w 00000000 epfr27 [r/w] b,h,w --- 0 ---- 000e7c h epfr28 [r/w] b,h,w -- 000 - 0 - epfr29 [r/w] b,h,w 00000000 D D 000e80 h D epfr33 [r/w] b,h,w ----- 00 - epfr34 [r/w] b,h,w ----- 00 - epfr35 [r/w] b, h,w --- 00000 000e84 h epfr36 [r/w] b,h,w ---- 000 - D D D 000e88 h D D epfr42 [r/w] b,h,w ------ 00 epfr43 [r/w] b,h,w 0 -- 0000 - 000e8c h epfr44 [r/w] b,h,w - 00 --- 0 - epfr45 [r/w] b,h,w - 0000000 D D 000e90 h D D D D 000e94 h D D D D 000e98 h epfr56 [ r/w] b,h,w ----- 0 - 0 epfr57 [r/w] b,h,w ---- 00 - 0 epfr58 [r/w] b,h,w ---- 00 - 0 epfr59 [r/w] b,h,w ---- 00 - 0 000e9c h epfr60 [r/w] b,h,w ---- 00 - 0 epfr61 [r/w] b,h,w ----- 00 - epfr62 [r/w] b,h,w ----- 00 - epfr63 [r/w] b,h,w --- 0000 - 000ea0 h to 000ebc h D D D D reserved 000ec0 h pper00 [r/w] b,h,w 00000000 pper01 [r/w] b,h,w 00000000 pper02 [r/w] b,h,w 00000000 pper03 [r/w] b,h,w 00000000 port pull - up/down enable register 000ec4 h pper04 [r/w] b,h,w 00000000 pper05 [r/w] b,h,w 00000000 pper06 [r/w] b,h,w 0 0000000 pper07 [r/w] b,h,w 00000000 000ec8 h pper08 [r/w] b,h,w 00000000 pper09 [r/w] b,h,w 00000000 pper10 [r/w] b,h,w 00000000 pper11 [r/w] b,h,w 00000000 000ecc h pper12 [r/w] b,h,w 00000000 pper13 [r/w] b,h,w - 0000000 pper14 [r/w] b,h,w --- 000 -- pper 15 [r/w] b,h,w -- 000000 000ed0 h D D D D 000ed4 h D D D D 000ed8 h pper16 [r/w] b,h,w 00000000 pper17 [r/w] b,h,w 00000000 pper18 [r/w] b,h,w 00000000 pper19 [r/w] b,h,w 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 71 confidential address address offset value / register name block +0 +1 +2 +3 000edc h to 000f3c h D D D D reserved 000f40 h porten [r/w] b,h,w ------- 0 D D D port enable registe r 000f44 h keycdr [r/w] h 00000000 00000000 D D keycoderegister 000f48 h to 000f64 h D D D D reserved 000f68 h mscy6 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 6,7 cycle measurement data register 67 000f6c h mscy7 [r] h,w xxxxxxxx xxxxxxxx xx xxxxxx xxxxxxxx 000f70 h rcrh0 [w] h,w xxxxxxxx rcrl0 [w] b,h,w xxxxxxxx udcrh0 [r] h,w 00000000 udcrl0 [r] b,h,w 00000000 up/down counter 0 000f74 h ccr0 [r/w] b,h 00000000 - 0001000 D csr0 [r/w] b 00000000 000f78 h to 000f7c h D D D D reserved 000f80 h r crh1 [w] h,w xxxxxxxx rcrl1 [w] b,h,w xxxxxxxx udcrh1 [r] h,w 00000000 udcrl1 [r] b,h,w 00000000 up/down counter 1 000f84 h ccr1 [r/w] b,h 00000000 - 0001000 D csr1 [r/w] b 00000000 000f88 h D D msch45 [r] b,h,w 00000000 mscl45 [r/w] b,h,w ------ 00 inpu t capture 4,5 32 - bit icu cycle and pulse width measurement control 45 000f8c h D D msch67 [r] b,h,w 00000000 mscl67 [r/w] b,h,w ------ 00 input capture 6,7 32 - bit icu cycle and pulse width measurement control 67 000f90 h occp10 [r/w] w 00000000 00000000 0 0000000 00000000 output compare 10,11 32 - bit ocu 000f94 h occp11 [r/w] w 00000000 00000000 00000000 00000000 000f98 h D D ocsh1011 [r/w] b,h,w --- 0 -- 00 ocsl1011 [r/w] b,h,w 0000 -- 00 000f9c h D D D ocls1011 [r/w] b,h,w ---- 0000 ocu1011 output level control register d a t a s h e e t 72 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 000fa0 h cpclr5 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 5 32 - bit frt 000fa4 h tcdt5 [r/w] w 00000000 00000000 00000000 00000000 000fa8 h tccsh5 [r/w]b,h,w 0 ----- 00 tccsl5 [r/w]b,h,w - 1 - 00000 D D 000fac h to 000fcc h D D D D reserved 000fd0 h ipcp4 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 4,5 32 - bit icu 000fd4 h ipcp5 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000fd8 h D D lsyns1 [r/w] b,h,w 00000000 ics45 [r/w] b,h,w 00000000 000fdc h ipcp6 [r] w xxxxxxx x xxxxxxxx xxxxxxxx xxxxxxxx input capture 6,7 32 - bit icu 000fe0 h ipcp7 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000fe4 h D D D ics67 [r/w] b,h,w 00000000 000fe8 h ipcp8 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 8,9 32 - bit icu 000fec h ip cp9 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ff0 h D D D ics89 [r/w] b,h,w 00000000 000ff4 h mscy8 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 8,9 32 - bit icu cycle measurement data register 89 000ff8 h mscy9 [r] h,w xxxxxxxx xxxxxxxx xx xxxxxx xxxxxxxx 000ffc h D D msch89 [r] b,h,w 00000000 mscl89 [r/w] b,h,w ------ 00 cycle and pulse width measurement control 89 001000 h sacr [r/w] b,h,w ------- 0 picd [r/w] b,h,w ---- 0011 D D clock control 001004 h to 00112c h D D D D reserved 001130 h D D D crccr [r/w] b,h,w - 0000000 crc calculation unit 001134 h crcinit [r/w] b,h,w 11111111 11111111 11111111 11111111 001138 h crcin [r/w] b,h,w 00000000 00000000 00000000 00000000 00113c h crcr [r] b,h,w 11111111 11111111 11111111 11111111 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 73 confidential address address offset value / register name block +0 +1 +2 +3 001140 h to 0 011fc h D D D D reserved 001200 h tcgs [r/w] b,h,w ------ 00 D D tcgse [r/w] b,h,w ----- 000 16 - bit free - run timer synchronous activation 001204 h cpclrb0/cpclr0 [w] h,w 11111111 11111111 tcdt0 [r/w] h,w 00000000 00000000 16 - bit free - run timer 0 001208 h tccs 0 [r/w] b,h,w 00000000 01000000 ---- 0000 -------- 00120c h cpclrb1/cpclr1 [w] h,w 11111111 11111111 tcdt1 [r/w] h,w 00000000 00000000 16 - bit free - run timer 1 001210 h tccs1 [r/w] b,h,w 00000000 01000000 ---- 0000 -------- 001214 h cpclrb2/cpclr2 [w] h,w 1 1111111 11111111 tcdt2 [r/w] h,w 00000000 00000000 16 - bit free - run timer 2 001218 h tccs2 [r/w] b,h,w 00000000 01000000 ---- 0000 -------- 00121c h to 001230 h D D D D reserved 001234 h frs0 [r/w] b,h,w -------- -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 16 - bit free - run timer selection 001238 h D frs1 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 00123c h frs2 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 001240 h frs3 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 001244 h frs4 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 001248 h D D D D reserved 00124c h occpb0/occp0 [r/w] h,w 00000000 00000000 occpb1/occp1 [r/w] h,w 00000000 00000000 16 - bit output compare 0/1 001250 h ocs01 [r/w] b ,h,w - 110 -- 00 00001100 D ocmod01 [r/w] b,h,w ------ 00 001254 h occpb2/occp2 [r/w] h,w 00000000 00000000 occpb3/occp3 [r/w] h,w 00000000 00000000 16 - bit output compare 2/3 001258 h ocs23 [r/w] b,h,w - 110 -- 00 00001100 D ocmod23 [r/w] b,h,w ------ 00 0012 5c h occpb4/occp4 [r/w] h,w 00000000 00000000 occpb5/occp5 [r/w] h,w 00000000 00000000 16 - bit output compare 4/5 001260 h ocs45 [r/w] b,h,w - 110 -- 00 00001100 D ocmod45 [r/w] b,h,w ------ 00 d a t a s h e e t 74 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001264 h to 001278 h D D D D reserved 00127c h ipcp0 [r] h,w 0000 0000 00000000 ipcp1 [r] h,w 00000000 00000000 16 - bit input capture 0/1 001280 h ics01 [r/w] b,h,w ------ 00 00000000 D lsyns [r/w] b,h,w ---- 0000 001284 h ipcp2 [r] h,w 00000000 00000000 ipcp3 [r] h,w 00000000 00000000 16 - bit input capture 2/3 001288 h ics 23 [r/w] b,h,w ------ 00 00000000 D D 00128c h to 001298 h D D D D reserved 00129c h D D D D reserved 0012a0 h tmrr0 [r/w] h,w 00000000 00000001 tmrr1 [r/w] h,w 00000000 00000001 waveform generator 0/1/2 0012a4 h tmrr2 [r/w] h,w 00000000 00000001 D D 001 2a8 h dtscr0 [r/w] b,h,w 00000000 dtscr1 [r/w] b,h,w 00000000 dtscr2 [r/w] b,h,w 00000000 D 0012ac h D dtir0 [r/w] b,h,w 000000 -- D dtmns0 [r/w] b,h,w 00 --- 000 0012b0 h D sigcr10 [r/w] b,h,w 00000000 D sigcr20 [r/w] b,h,w 000000 - 1 0012b4 h pics0 [r/w] b,h,w 000000 -- -------- -------- -------- 0012b8 h to 0012cc h D D D D reserved 0012d0 h frs5 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 16 - bit free - run timer selection a/d activation compare 0012d4 h frs6 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 - - 00 0012d8 h frs7 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 0012dc h to 0012fc h D D D D reserved 001300 h D reserved 001304 h adtss0[r/w] b,h,w ------- 0 D D D 12 - bit a/d converter 1/2 unit 001308 h adtse0[r/w] b,h,w 00000000 00000000 00000000 0000 0000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 75 confidential address address offset value / register name block +0 +1 +2 +3 00130c h adcomp0/adcompb0[r/w] h,w 00000000 00000000 adcomp1/adcompb1[r/w] h,w 00000000 00000000 12 - bit a/d converter 1/2 unit 001310 h adcomp2/adcompb2[r/w] h,w 00000000 00000000 adcomp3/adcompb3[r/w] h,w 00000000 00000000 001314 h adcomp4/adcompb4 [r/w] h,w 00000000 00000000 adcomp5/adcompb5[r/w] h,w 00000000 00000000 001318 h adcomp6/adcompb6[r/w] h,w 00000000 00000000 adcomp7/adcompb7[r/w] h,w 00000000 00000000 00131c h adcomp8/adcompb8[r/w] h,w 00000000 00000000 adcomp9/adcompb9[r/w] h,w 000000 00 00000000 001320 h adcomp10/adcompb10[r/w] h,w 00000000 00000000 adcomp11/adcompb11[r/w] h,w 00000000 00000000 001324 h adcomp12/adcompb12[r/w] h,w 00000000 00000000 adcomp13/adcompb13[r/w] h,w 00000000 00000000 001328 h adcomp14/adcompb14[r/w] h,w 00 000000 00000000 adcomp15/adcompb15[r/w] h,w 00000000 00000000 00132c h adcomp16/adcompb16[r/w] h,w 00000000 00000000 adcomp17/adcompb17[r/w] h,w 00000000 00000000 001330 h adcomp18/adcompb18[r/w] h,w 00000000 00000000 adcomp19/adcompb19[r/w] h,w 00000000 00000000 001334 h adcomp20/adcompb20[r/w] h,w 00000000 00000000 adcomp21/adcompb21[r/w] h,w 00000000 00000000 001338 h adcomp22/adcompb22[r/w] h,w 00000000 00000000 adcomp23/adcompb23[r/w] h,w 00000000 00000000 00133c h adcomp24/adcompb24[r/w] h,w 0000 0000 00000000 adcomp25/adcompb25[r/w] h,w 00000000 00000000 001340 h adcomp26/adcompb26[r/w] h,w 00000000 00000000 adcomp27/adcompb27[r/w] h,w 00000000 00000000 001344 h adcomp28/adcompb28[r/w] h,w 00000000 00000000 adcomp29/adcompb29[r/w] h,w 00000000 0 0000000 001348 h adcomp30/adcompb30[r/w] h,w 00000000 00000000 adcomp31/adcompb31[r/w] h,w 00000000 00000000 00134c h adtcs0[r/w] b,h,w 00000000 0010 ---- adtcs1[r/w] b,h,w 00000000 0010 ---- 001350 h adtcs2[r/w] b,h,w 00000000 0010 ---- adtcs3[r/w] b,h,w 00000000 0010 ---- 001354 h adtcs4[r/w] b,h,w 00000000 0010 ---- adtcs5[r/w] b,h,w 00000000 0010 ---- 001358 h adtcs6[r/w] b,h,w 00000000 0010 ---- adtcs7[r/w] b,h,w 00000000 0010 ---- 00135c h adtcs8[r/w] b,h,w 00000000 0010 ---- adtcs9[r/w] b,h,w 00000000 0 010 ---- 001360 h adtcs10[r/w] b,h,w 00000000 0010 ---- adtcs11[r/w] b,h,w 00000000 0010 ---- d a t a s h e e t 76 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001364 h adtcs12[r/w] b,h,w 00000000 0010 ---- adtcs13[r/w] b,h,w 00000000 0010 ---- 12 - bit a/d converter 1/2 unit 001368 h adtcs14[r/w] b,h,w 00000000 0010 ---- adtc s15[r/w] b,h,w 00000000 0010 ---- 00136c h adtcs16[r/w] b,h,w 00000000 0010 ---- adtcs17[r/w] b,h,w 00000000 0010 ---- 001370 h adtcs18[r/w] b,h,w 00000000 0010 ---- adtcs19[r/w] b,h,w 00000000 0010 ---- 001374 h adtcs20[r/w] b,h,w 00000000 0010 ---- adtcs21[ r/w] b,h,w 00000000 0010 ---- 001378 h adtcs22[r/w] b,h,w 00000000 0010 ---- adtcs23[r/w] b,h,w 00000000 0010 ---- 00137c h adtcs24[r/w] b,h,w 00000000 0010 ---- adtcs25[r/w] b,h,w 00000000 0010 ---- 001380 h adtcs26[r/w] b,h,w 00000000 0010 ---- adtcs27[r/w] b,h,w 00000000 0010 ---- 001384 h adtcs28[r/w] b,h,w 00000000 0010 ---- adtcs29[r/w] b,h,w 00000000 0010 ---- 001388 h adtcs30[r/w] b,h,w 00000000 0010 ---- adtcs31[r/w] b,h,w 00000000 0010 ---- 00138c h adtcd0[r] b,h,w 10 -- 0000 00000000 adtcd1[r] b,h,w 10 - - 0000 00000000 001390 h adtcd2[r] b,h,w 10 -- 0000 00000000 adtcd3[r] b,h,w 10 -- 0000 00000000 001394 h adtcd4[r] b,h,w 10 -- 0000 00000000 adtcd5[r] b,h,w 10 -- 0000 00000000 001398 h adtcd6[r] b,h,w 10 -- 0000 00000000 adtcd7[r] b,h,w 10 -- 0000 00000000 00139 c h adtcd8[r] b,h,w 10 -- 0000 00000000 adtcd9[r] b,h,w 10 -- 0000 00000000 0013a0 h adtcd10[r] b,h,w 10 -- 0000 00000000 adtcd11[r] b,h,w 10 -- 0000 00000000 0013a4 h adtcd12[r] b,h,w 10 -- 0000 00000000 adtcd13[r] b,h,w 10 -- 0000 00000000 0013a8 h adtcd14[r] b,h, w 10 -- 0000 00000000 adtcd15[r] b,h,w 10 -- 0000 00000000 0013ac h adtcd16[r] b,h,w 10 -- 0000 00000000 adtcd17[r] b,h,w 10 -- 0000 00000000 0013b0 h adtcd18[r] b,h,w 10 -- 0000 00000000 adtcd19[r] b,h,w 10 -- 0000 00000000 0013b4 h adtcd20[r] b,h,w 10 -- 0000 00000 000 adtcd21[r] b,h,w 10 -- 0000 00000000 0013b8 h adtcd22[r] b,h,w 10 -- 0000 00000000 adtcd23[r] b,h,w 10 -- 0000 00000000 0013bc h adtcd24[r] b,h,w 10 -- 0000 00000000 adtcd25[r] b,h,w 10 -- 0000 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 77 confidential address address offset value / register name block +0 +1 +2 +3 0013c0 h adtcd26[r] b,h,w 10 -- 0000 00000000 adtcd27[r] b ,h,w 10 -- 0000 00000000 12 - bit a/d converter 1/2 unit 0013c4 h adtcd28[r] b,h,w 10 -- 0000 00000000 adtcd29[r] b,h,w 10 -- 0000 00000000 0013c8 h adtcd30[r] b,h,w 10 -- 0000 00000000 adtcd31[r] b,h,w 10 -- 0000 00000000 0013cc h adtecs0[r/w] b,h,w ------- 0 --- 000 00 adtecs1[r/w] b,h,w ------- 0 --- 00000 0013d0 h adtecs2[r/w] b,h,w ------- 0 --- 00000 adtecs3[r/w] b,h,w ------- 0 --- 00000 0013d4 h adtecs4[r/w] b,h,w ------- 0 --- 00000 adtecs5[r/w] b,h,w ------- 0 --- 00000 0013d8 h adtecs6[r/w] b,h,w ------- 0 --- 00000 a dtecs7[r/w] b,h,w ------- 0 --- 00000 0013dc h adtecs8[r/w] b,h,w ------- 0 --- 00000 adtecs9[r/w] b,h,w ------- 0 --- 00000 0013e0 h adtecs10[r/w] b,h,w ------- 0 --- 00000 adtecs11[r/w] b,h,w ------- 0 --- 00000 0013e4 h adtecs12[r/w] b,h,w ------- 0 --- 00000 ad tecs13[r/w] b,h,w ------- 0 --- 00000 0013e8 h adtecs14[r/w] b,h,w ------- 0 --- 00000 adtecs15[r/w] b,h,w ------- 0 --- 00000 0013ec h adtecs16[r/w] b,h,w ------- 0 --- 00000 adtecs17[r/w] b,h,w ------- 0 --- 00000 0013f0 h adtecs18[r/w] b,h,w ------- 0 --- 00000 adtecs19[r/w] b,h,w ------- 0 --- 00000 0013f4 h adtecs20[r/w] b,h,w ------- 0 --- 00000 adtecs21[r/w] b,h,w ------- 0 --- 00000 0013f8 h adtecs22[r/w] b,h,w ------- 0 --- 00000 adtecs23[r/w] b,h,w ------- 0 --- 00000 0013fc h adtecs24[r/w] b,h,w ------- 0 --- 0000 0 adtecs25[r/w] b,h,w ------- 0 --- 00000 001400 h adtecs26[r/w] b,h,w ------- 0 --- 00000 adtecs27[r/w] b,h,w ------- 0 --- 00000 001404 h adtecs28[r/w] b,h,w ------- 0 --- 00000 adtecs29[r/w] b,h,w ------- 0 --- 00000 001408 h adtecs30[r/w] b,h,w ------- 0 --- 00 000 adtecs31[r/w] b,h,w ------- 0 --- 00000 00140c h adrcut0[r/w] b,h,w ---- 0000 00000000 adrclt0[r/w] b,h,w ---- 0000 00000000 001410 h adrcut1[r/w] b,h,w ---- 0000 00000000 adrclt1[r/w] b,h,w ---- 0000 00000000 001414 h adrcut2[r/w] b,h,w ---- 0000 00000000 adrclt2[r/w] b,h,w ---- 0000 00000000 001418 h adrcut3[r/w] b,h,w ---- 0000 00000000 adrclt3[r/w] b,h,w ---- 0000 00000000 d a t a s h e e t 78 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 00141c h adrccs0[r/w] b,h,w 00000000 adrccs1[r/w] b,h,w 00000000 adrccs2[r/w] b,h,w 00000000 adrccs3[r/w] b,h,w 00000000 12 - bit a /d converter 1/2 unit 001420 h adrccs4[r/w] b,h,w 00000000 adrccs5[r/w] b,h,w 00000000 adrccs6[r/w] b,h,w 00000000 adrccs7[r/w] b,h,w 00000000 001424 h adrccs8[r/w] b,h,w 00000000 adrccs9[r/w] b,h,w 00000000 adrccs10[r/w] b,h,w 00000000 adrccs11[r/ w] b,h,w 00000000 001428 h adrccs12[r/w] b,h,w 00000000 adrccs13[r/w] b,h,w 00000000 adrccs14[r/w] b,h,w 00000000 adrccs15[r/w] b,h,w 00000000 00142c h adrccs16[r/w] b,h,w 00000000 adrccs17[r/w] b,h,w 00000000 adrccs18[r/w] b,h,w 00000000 adrccs1 9[r/w] b,h,w 00000000 001430 h adrccs20[r/w] b,h,w 00000000 adrccs21[r/w] b,h,w 00000000 adrccs22[r/w] b,h,w 00000000 adrccs23[r/w] b,h,w 00000000 001434 h adrccs24[r/w] b,h,w 00000000 adrccs25[r/w] b,h,w 00000000 adrccs26[r/w] b,h,w 00000000 adr ccs27[r/w] b,h,w 00000000 001438 h adrccs28[r/w] b,h,w 00000000 adrccs29[r/w] b,h,w 00000000 adrccs30[r/w] b,h,w 00000000 adrccs31[r/w] b,h,w 00000000 00143c h adrcot0[r] b,h,w 00000000 00000000 00000000 00000000 001440 h adrcif0[r,w] b,h,w 0000000 0 00000000 00000000 00000000 001444 h adscans0[r/w] b,h,w 000 ----- D D D 001448 h adncs0[r/w] b,h,w 0 - 000 - 00 adncs1[r/w] b,h,w 0 - 000 - 00 adncs2[r/w] b,h,w 0 - 000 - 00 adncs3[r/w] b,h,w 0 - 000 - 00 00144c h adncs4[r/w] b,h,w 0 - 000 - 00 adncs5[r/w] b,h,w 0 - 000 - 00 adncs6[r/w] b,h,w 0 - 000 - 00 adncs7[r/w] b,h,w 0 - 000 - 00 001450 h adncs8[r/w] b,h,w 0 - 000 - 00 adncs9[r/w] b,h,w 0 - 000 - 00 adncs10[r/w] b,h,w 0 - 000 - 00 adncs11[r/w] b,h,w 0 - 000 - 00 001454 h adncs12[r/w] b,h,w 0 - 000 - 00 adncs13[r/w] b,h,w 0 - 000 - 00 adncs14[r/w] b, h,w 0 - 000 - 00 adncs15[r/w] b,h,w 0 - 000 - 00 001458 h adprtf0[r] b,h,w 00000000 00000000 00000000 00000000 00145c h adeocf0[r] b,h,w 11111111 11111111 11111111 11111111 001460 h adcs0[r] b,h,w 0 ------- -------- adch0[r] b,h,w --- 00000 admd0[r/w] b,h,w 0 --- 0 000 001464 h adstpcs0[r/w] b,h,w 00000000 adstpcs1[r/w] b,h,w 00000000 adstpcs2[r/w] b,h,w 00000000 adstpcs3[r/w] b,h,w 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 79 confidential address address offset value / register name block +0 +1 +2 +3 001468 h adstpcs4[r/w] b,h,w 00000000 adstpcs5[r/w] b,h,w 00000000 adstpcs6[r/w] b,h,w 00000000 adstpcs7[r/w] b,h,w 0 0000000 12 - bit a/d converter 1/2 unit 00146c h D 12 - bit a/d converter 2/2 unit 001470 h adtss1[r/w] b,h,w ------- 0 D D D 001474 h adtse1[r/w] b,h,w -------- -------- 00000000 00000000 001478 h adcomp32/adcompb32[r/w] h,w 00000000 00000000 adcomp33/adcompb33[r/w] h,w 00000000 00000000 00147c h adcom p34/adcompb34[r/w] h,w 00000000 00000000 adcomp35/adcompb35[r/w] h,w 00000000 00000000 001480 h adcomp36/adcompb36[r/w] h,w 00000000 00000000 adcomp37/adcompb37[r/w] h,w 00000000 00000000 001484 h adcomp38/adcompb38[r/w] h,w 00000000 00000000 adcomp39/ad compb39[r/w] h,w 00000000 00000000 001488 h adcomp40/adcompb40[r/w] h,w 00000000 00000000 adcomp41/adcompb41[r/w] h,w 00000000 00000000 00148c h adcomp42/adcompb42[r/w] h,w 00000000 00000000 adcomp43/adcompb43[r/w] h,w 00000000 00000000 001490 h adcomp4 4/adcompb44[r/w] h,w 00000000 00000000 adcomp45/adcompb45[r/w] h,w 00000000 00000000 001494 h adcomp46/adcompb46[r/w] h,w 00000000 00000000 adcomp47/adcompb47[r/w] h,w 00000000 00000000 001498 h to 0014b4 h D D D D reserved 0014b8 h adtcs32[r/w] b,h,w 00 000000 0010 ---- adtcs33[r/w] b,h,w 00000000 0010 ---- 12 - bit a/d converter 2/2 unit 0014bc h adtcs34[r/w] b,h,w 00000000 0010 ---- adtcs35[r/w] b,h,w 00000000 0010 ---- 0014c0 h adtcs36[r/w] b,h,w 00000000 0010 ---- adtcs37[r/w] b,h,w 00000000 0010 ---- 0014 c4 h adtcs38[r/w] b,h,w 00000000 0010 ---- adtcs39[r/w] b,h,w 00000000 0010 ---- 0014c8 h adtcs40[r/w] b,h,w 00000000 0010 ---- adtcs41[r/w] b,h,w 00000000 0010 ---- 0014cc h adtcs42[r/w] b,h,w 00000000 0010 ---- adtcs43[r/w] b,h,w 00000000 0010 ---- 0014d0 h adtcs44[r/w] b,h,w 00000000 0010 ---- adtcs45[r/w] b,h,w 00000000 0010 ---- 0014d4 h adtcs46[r/w] b,h,w 00000000 0010 ---- adtcs47[r/w] b,h,w 00000000 0010 ---- d a t a s h e e t 80 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0014d8 h to 0014f4 h D D D D reserved 0014f8 h adtcd32[r] b,h,w 10 -- 0000 00000000 adtcd33[r] b,h,w 10 -- 0000 00000000 12 - bit a/d converter 2/2 unit 0014fc h adtcd34[r] b,h,w 10 -- 0000 00000000 adtcd35[r] b,h,w 10 -- 0000 00000000 001500 h adtcd36[r] b,h,w 10 -- 0000 00000000 adtcd37[r] b,h,w 10 -- 0000 00000000 001504 h adtcd38[r] b,h,w 10 -- 0000 000000 00 adtcd39[r] b,h,w 10 -- 0000 00000000 001508 h adtcd40[r] b,h,w 10 -- 0000 00000000 adtcd41[r] b,h,w 10 -- 0000 00000000 00150c h adtcd42[r] b,h,w 10 -- 0000 00000000 adtcd43[r] b,h,w 10 -- 0000 00000000 001510 h adtcd44[r] b,h,w 10 -- 0000 00000000 adtcd45[r] b, h,w 10 -- 0000 00000000 001514 h adtcd46[r] b,h,w 10 -- 0000 00000000 adtcd47[r] b,h,w 10 -- 0000 00000000 001518 h to 001534 h D D D D reserved 001538 h adtecs32[r/w] b,h,w ------- 0 ---- 0000 adtecs33[r/w] b,h,w ------- 0 ---- 0000 12 - bit a/d converter 2/2 unit 00153c h adtecs34[r/w] b,h,w ------- 0 ---- 0000 adtecs35[r/w] b,h,w ------- 0 ---- 0000 001540 h adtecs36[r/w] b,h,w ------- 0 ---- 0000 adtecs37[r/w] b,h,w ------- 0 ---- 0000 001544 h adtecs38[r/w] b,h,w ------- 0 ---- 0000 adtecs39[r/w] b,h,w ------- 0 ---- 0000 001548 h adtecs40[r/w] b,h,w ------- 0 ---- 0000 adtecs41[r/w] b,h,w ------- 0 ---- 0000 00154c h adtecs42[r/w] b,h,w ------- 0 ---- 0000 adtecs43[r/w] b,h,w ------- 0 ---- 0000 001550 h adtecs44[r/w] b,h,w ------- 0 ---- 0000 adtecs45[r/w] b,h,w ------- 0 ---- 00 00 001554 h adtecs46[r/w] b,h,w ------- 0 ---- 0000 adtecs47[r/w] b,h,w ------- 0 ---- 0000 001558 h to 001574 h D D D D reserved 001578 h adrcut4[r/w] b,h,w ---- 0000 00000000 adrclt4[r/w] b,h,w ---- 0000 00000000 12 - bit a/d converter 2/2 unit 00157c h adrcut 5[r/w] b,h,w ---- 0000 00000000 adrclt5[r/w] b,h,w ---- 0000 00000000 001580 h adrcut6[r/w] b,h,w ---- 0000 00000000 adrclt6[r/w] b,h,w ---- 0000 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 81 confidential address address offset value / register name block +0 +1 +2 +3 001584 h adrcut7[r/w] b,h,w ---- 0000 00000000 adrclt7[r/w] b,h,w ---- 0000 00000000 12 - bit a/d converter 2/2 unit 001588 h adrccs32[r/w] b,h,w 00000000 adrccs33[r/w] b,h,w 00000000 adrccs34[r/w] b,h,w 00000000 adrccs35[r/w] b,h,w 00000000 00158c h adrccs36[r/w] b,h,w 00000000 adrccs37[r/w] b,h,w 00000000 adrccs38[r/w] b,h,w 00000000 adrccs39[r/w] b, h,w 00000000 001590 h adrccs40[r/w] b,h,w 00000000 adrccs41[r/w] b,h,w 00000000 adrccs42[r/w] b,h,w 00000000 adrccs43[r/w] b,h,w 00000000 001594 h adrccs44[r/w] b,h,w 00000000 adrccs45[r/w] b,h,w 00000000 adrccs46[r/w] b,h,w 00000000 adrccs47[r/w] b,h,w 00000000 001598 h to 0015a4 h D D D D reserved 0015a8 h adrcot1 [r] b,h,w -------- -------- 00000000 00000000 12 - bit a/d converter 2/2 unit 0015ac h adrcif1 [r,w] b,h,w -------- -------- 00000000 00000000 0015b0 h adscans1 [r/w] b,h,w 000 ----- D D D 0015b4 h adncs16 [r/w] b,h,w 0 - 0 00 - 00 adncs17 [r/w] b,h,w 0 - 000 - 00 adncs18 [r/w] b,h,w 0 - 000 - 00 adncs19 [r/w] b,h,w 0 - 000 - 00 0015b8 h adncs20 [r/w] b,h,w 0 - 000 - 00 adncs21 [r/w] b,h,w 0 - 000 - 00 adncs22 [r/w] b,h,w 0 - 000 - 00 adncs23 [r/w] b,h,w 0 - 000 - 00 0015bc h D D D D 0015c0 h D D D D 0015c4 h adprtf1 [r] b,h,w -------- -------- 00000000 00000000 0015c8 h adeocf1 [r] b,h,w -------- -------- 11111111 11111111 0015cc h adcs1 [r] b,h,w 0 ------- -------- adch1 [r] b,h,w --- 00000 admd1 [r/w] b,h,w 0 --- 0000 0015d0 h adstpcs8 [r/w] b,h,w 00000000 adstpcs9 [r/w] b,h,w 00000000 adstpcs10 [r/w] b,h,w 00000000 adstpcs11 [r/w] b,h,w 00000000 d a t a s h e e t 82 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0015d4 h to 00174c h D D D D reserved 001750 h scr0/(ibcr0)[r/w] b,h,w 0 -- 00000 smr0[r/w] b,h,w 000 - 00 - 0 ssr0[r/w] b,h,w 0 - 000011 escr0 /(ibsr0)[r/w] b,h,w 00000000 multi - uart0 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved becau se lin2.1 mode is not set immediately after reset. 001754 h D /(rdr10/(tdr10))[r/w] b, h,w -------- -------- *3 rdr00/(tdr00)[r/w] b,h,w ------- 0 00000000 *1 001758 h sacsr0[r/w] b,h,w 0 ---- 000 00000000 stmr0[r] b,h,w 00000000 00000000 00175c h stmcr0[r/w] b,h,w 00000000 00000000 D /(scscr0/sfur0)[r/w] b,h,w ----- --- -------- *3 *4 001760 h D /(scstr30)/ (lamsr0) [r/w] b,h,w -------- *3 D /(scstr20)/ (lamcr0) [r/w] b,h,w -------- *3 D /(scstr10) /(sflr10) [r/w] b,h,w -------- *3 D /(scstr00)/ (sflr00) [r/w] b,h,w -------- *3 001764 h D D /(scsfr20) [r/w] b,h,w - ------- *3 D /(scsfr10) [r/w] b,h,w -------- *3 D /(scsfr00) [r/w] b,h,w -------- *3 001768 h D/(tbyte30)/ (lamesr0) [r/w] b,h,w -------- *3 D/(tbyte20) /(lamert0) [r/w] b,h,w -------- *3 D/(tbyte10)/ (lamier0) [r/w] b,h,w -------- *3 tbyte00/(lamrid0) / (lamtid0) [r/w] b,h,w 00000000 00176c h bgr0[r/w] h, w 00000000 00000000 D /(ismk0) [r/w] b,h,w -------- *2 D /(isba0) [r/w] b,h,w -------- *2 001770 h fcr10[r/w] b,h,w --- 00100 fcr00[r/w] b,h,w - 0000000 fbyte0[r/w] b,h,w 00000000 00000000 001774 h ft icr0[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 83 confidential address address offset value / register name block +0 +1 +2 +3 001778 h scr1/(ibcr1) [r/w] b,h,w 0 -- 00000 smr1[r/w] b,h,w 000 - 00 - 0 ssr1[r/w] b,h,w 0 - 000011 escr1/(ibsr1)[r/w] b,h,w 00000000 multi - uart1 *1 : byte access is possible only for access to lower 8 b its. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 00177c h D /(rdr11/(tdr11))[r/w] b, h,w ------- - -------- *3 rdr01/(tdr01)[r/w] b,h,w ------- 0 00000000 *1 001780 h sacsr1[r/w] b,h,w 0 ---- 000 00000000 stmr1[r] b,h,w 00000000 00000000 001784 h stmcr1[r/w] b,h,w 00000000 00000000 D /(scscr1/sfur1)[r/w] b,h,w -------- -------- *3 *4 001788 h D /(scst r31)/ (lamsr1) [r/w] b,h,w -------- *3 D /(scstr21)/ (lamcr1) [r/w] b,h,w -------- *3 D /(scstr11)/ (sflr11) [r/w] b,h,w -------- *3 D /(scstr01)/ (sflr01) [r/w] b,h,w -------- *3 00178c h D D /(scsfr21)[r/w] b,h,w -------- *3 D /(scsfr11) [r/w] b,h,w -------- *3 D /(scsfr01) [r/w] b,h,w -------- *3 001790 h D/(tbyte31)/ (lamesr1) [r/w] b,h,w -------- *3 D/(tbyte21)/ (lamert1) [r/w] b,h,w -------- *3 D/(tbyte11)/ (lamier1) [r/w] b,h,w -------- *3 tbyte01/(lamrid1) / (lamtid1) [r/w] b,h,w 00000000 00 1794 h bgr1[r/w] h,w 00000000 00000000 D /(ismk1)[r/w] b,h,w -------- *2 D /(isba1)[r/w] b,h,w -------- *2 001798 h fcr11[r/w] b,h,w --- 00100 fcr01[r/w] b,h,w - 0000000 fbyte1[r/w] b,h,w 00000000 00000000 00179c h fticr1[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 84 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0017a0 h scr2/(ibcr2)[r/w] b,h,w 0 -- 00000 smr2[r/w] b,h,w 000 - 00 - 0 ssr2[r/w] b,h,w 0 - 000011 escr2/(ibsr2)[r/w] b,h,w 00000000 multi - uart2 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 0017a4 h D /(rdr12/(tdr12))[r/w] b, h,w -------- -------- *3 rdr02/(tdr02)[r/w] b,h,w ------- 0 00000000 *1 0017a8 h sacsr2[r/w] b,h,w 0 ---- 000 00000000 stmr2[r] b,h,w 00000000 00000000 0017ac h stmcr2[r/w] b,h,w 00000000 00000000 D /(scscr2/sfur2)[r/w] b,h,w ----- --- -------- *3 *4 0017b0 h D /(scstr32)/ (lamsr2) [r/w] b,h,w -------- *3 D /(scstr22)/ (lamcr2) [r/w] b,h,w -------- *3 D /(scstr12)/ (sflr12) [r/w] b,h,w -------- *3 D /(scstr02)/ (sflr02) [r/w] b,h,w -------- *3 0017b4 h D D /(scsfr22) [r/w] b,h,w -------- *3 D /(scsfr12) [r/w] b,h,w -------- *3 D /(scsfr02) [r/w] b,h,w -------- *3 0017b8 h D/(tbyte32)/ (lamesr2) [r/w] b,h,w -------- *3 D/(tbyte22)/ (lamert2) [r/w] b,h,w -------- *3 D/(tbyte12)/ (lamier2) [r/w] b,h,w -------- *3 tbyte02/(lamrid2) / (lamtid2) [r/w] b,h,w 00000000 0017bc h bgr2[r/w] h, w 00000000 00000000 D /(ismk2)[r/w] b,h,w -------- *2 D /(isba2)[r/w] b,h,w -------- *2 0017c0 h fcr12[r/w] b,h,w --- 00100 fcr02[r/w] b,h,w - 0000000 fbyte2[r/w] b,h,w 00000000 00000000 0017c4 h ft icr2[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 85 confidential address address offset value / register name block +0 +1 +2 +3 0017c8 h scr3/(ibcr3) [r/w] b,h,w 0 -- 00000 smr3[r/w] b,h,w 000 - 00 - 0 ssr3[r/w] b,h,w 0 - 000011 escr3/(ibsr3)[r/w] b,h,w 00000000 multi - uart3 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 0017cc h D /(rdr13/(tdr13))[r/w] b, h,w --- ----- -------- *3 rdr03/(tdr03)[r/w] b,h,w ------- 0 00000000 *1 0017d0 h sacsr3[r/w] b,h,w 0 ---- 000 00000000 stmr3[r] b,h,w 00000000 00000000 0017d4 h stmcr3[r/w] b,h,w 00000000 00000000 D /(scscr3/sfur3)[r/w] b,h,w -------- -------- *3 *4 0017d8 h D /( scstr33)/ (lamsr3) [r/w] b,h,w -------- *3 D /(scstr23)/ (lamcr3) [r/w] b,h,w -------- *3 D /(scstr13)/ (sflr13) [r/w] b,h,w -------- *3 D /(scstr03)/ (sflr03) [r/w] b,h,w -------- *3 0017dc h D D /(scsfr23) [r/w] b,h,w -------- *3 D /(scsfr13) [r/w] b ,h,w -------- *3 D /(scsfr03) [r/w] b,h,w -------- *3 0017e0 h D/(tbyte33)/ (lamesr3) [r/w] b,h,w -------- *3 D/(tbyte23)/ (lamert3) [r/w] b,h,w -------- *3 D/(tbyte13)/ (lamier3) [r/w] b,h,w -------- *3 tbyte03/(lamrid3) / (lamtid3) [r/w] b,h,w 00000000 0017e4 h bgr3[r/w] h, w 00000000 00000000 D /(ismk3)[r/w] b,h,w -------- *2 D /(isba3)[r/w] b,h,w -------- *2 0017e8 h fcr13[r/w] b,h,w --- 00100 fcr03[r/w] b,h,w - 0000000 fbyte3[r/w] b,h,w 00000000 00000000 0017ec h fticr3[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 86 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0017f0 h scr4/(ibcr4) [r/w] b,h,w 0 -- 00000 smr4[r/w] b,h,w 000 - 00 - 0 ssr4[r/w] b,h,w 0 - 000011 escr4/(ibsr4)[r/w] b,h,w 00000000 multi - uart4 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 0017f4 h D /(rdr14/(tdr14))[r/w] b, h,w -------- -------- *3 rdr04/(tdr04)[ r/w] b,h,w ------- 0 00000000 *1 0017f8 h sacsr4[r/w] b,h,w 0 ---- 000 00000000 stmr4[r] b,h,w 00000000 00000000 0017fc h stmcr4[r/w] b,h,w 00000000 00000000 D /(scscr4/sfur4)[r/w] b,h,w -------- -------- *3 *4 001800 h D /(scstr34)/ (lamsr4) [r/w] b,h,w -------- *3 D /(scstr24)/ (lamcr4) [r/w] b,h,w -------- *3 D /(scstr14)/ (sflr14) [r/w] b,h,w -------- *3 D /(scstr04)/ (sflr04) [r/w] b,h,w -------- *3 001804 h D D /(scsfr24) [r/w] b,h,w -------- *3 D /(scsfr14) [r/w] b,h,w -------- *3 D /(scsfr04) [r/ w] b,h,w -------- *3 001808 h D/(tbyte34)/ (lamesr4) [r/w] b,h,w -------- *3 D/(tbyte24)/ (lamert4) [r/w] b,h,w -------- *3 D/(tbyte14)/ (lamier4) [r/w] b,h,w -------- *3 tbyte04/(lamrid4) / (lamtid4) [r/w] b,h,w 00000000 00180c h bgr4[r/w] h, w 00000000 00000000 D /(ismk4)[r/w] b,h,w -------- *2 D /(isba4)[r/w] b,h,w -------- *2 001810 h fcr14[r/w] b,h,w --- 00100 fcr04[r/w] b,h,w - 0000000 fbyte4[r/w] b,h,w 00000000 00000000 001814 h fticr4[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 87 confidential address address offset value / register name block +0 +1 +2 +3 001818 h scr5/(ibcr5) [r/w] b,h,w 0 -- 00000 smr5[r/w] b,h,w 000 - 00 - 0 ssr5[r/w] b,h,w 0 - 000011 escr5/(ibsr5)[r/w] b,h,w 00000000 multi - uart5 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately aft er reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 00181c h D /(rdr15/(tdr15))[r/w] b, h,w -------- -------- *3 rdr05/(tdr05)[r/w] b,h,w ------- 0 00000000 *1 001820 h sacsr5[r/w] b,h,w 0 ---- 000 00000000 stmr5[r] b,h,w 00000000 00000000 001824 h stmcr5[r/w] b,h,w 00000000 00000000 D /(scscr5/sfur5)[r/w] b,h,w ----- --- -------- *3 *4 001828 h D /(scstr35)/ (lamsr5) [r/w] b,h,w -------- *3 D /(scstr25)/ (lamcr5) [r/w] b,h,w -------- *3 D /(scstr15)/ (sflr15) [r/w] b,h,w -------- *3 D /(scstr05)/ (sflr05) [r/w] b,h,w -------- *3 00182c h D D /(scsfr25) [r/w] b,h,w - ------- *3 D /(scsfr15) [r/w] b,h,w -------- *3 D /(scsfr05) [r/w] b,h,w -------- *3 001830 h D/(tbyte35)/ (lamesr5) [r/w] b,h,w -------- *3 D/(tbyte25)/ (lamert5) [r/w] b,h,w -------- *3 D/(tbyte15)/ (lamier5) [r/w] b,h,w -------- *3 tbyte05/(lamrid5) / (lamtid5) [r/w] b,h,w 00000000 001834 h bgr5[r/w] h, w 00000000 00000000 D /(ismk5)[r/w] b,h,w -------- *2 D /(isba5)[r/w] b,h,w -------- *2 001838 h fcr15[r/w] b,h,w --- 00100 fcr05[r/w] b,h,w - 0000000 fbyte5[r/w] b,h,w 00000000 00000000 00183c h ft icr5[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 88 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001840 h scr6/(ibcr6) [r/w] b,h,w 0 -- 00000 smr6[r/w] b,h,w 000 - 00 - 0 ssr6[r/w] b,h,w 0 - 000011 escr6/(ibsr6)[r/w] b,h,w 00000000 multi - uart6 *1 : byte access is possible only for access to lowe r 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 001844 h D /(rdr16/(tdr16))[r/w] b, h,w -- ------ -------- *3 rdr06/(tdr06)[r/w] b,h,w ------- 0 00000000 *1 001848 h sacsr6[r/w] b,h,w 0 ---- 000 00000000 stmr6[r] b,h,w 00000000 00000000 00184c h stmcr6[r/w] b,h,w 00000000 00000000 D /(scscr6/sfur6)[r/w] b,h,w -------- -------- *3 *4 001850 h D / (scstr36)/ (lamsr6) [r/w] b,h,w -------- *3 D /(scstr26)/ (lamcr6) [r/w] b,h,w -------- *3 D /(scstr16)/ (sflr16) [r/w] b,h,w -------- *3 D /(scstr06)/ (sflr06) [r/w] b,h,w -------- *3 001854 h D D /(scsfr26) [r/w] b,h,w -------- *3 D /(scsfr16) [r/w] b,h,w -------- *3 D /(scsfr06) [r/w] b,h,w -------- *3 001858 h D/(tbyte36)/ (lamesr6) [r/w] b,h,w -------- *3 D/(tbyte26)/ (lamert6) [r/w] b,h,w -------- *3 D/(tbyte16)/ (lamier6) [r/w] b,h,w -------- *3 tbyte06/(lamrid6) / (lamtid6) [r/w] b,h,w 00000000 00185c h bgr6[r/w] h, w 00000000 00000000 D /(ismk6)[r/w] b,h,w -------- *2 D /(isba6)[r/w] b,h,w -------- *2 001860 h fcr16[r/w] b,h,w --- 00100 fcr06[r/w] b,h,w - 0000000 fbyte6[r/w] b,h,w 00000000 00000000 001864 h fticr6[r/w] b,h,w 00000000 0000000 0 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 89 confidential address address offset value / register name block +0 +1 +2 +3 001868 h scr7/(ibcr7) [r/w] b,h,w 0 -- 00000 smr7[r/w] b,h,w 000 - 00 - 0 ssr7[r/w] b,h,w 0 - 000011 escr7/(ibsr7)[r/w] b,h,w 00000000 multi - uart7 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 00186c h D /(rdr17/(tdr17))[r/w] b, h,w -------- -------- *3 rdr07/(tdr07) [r/w] b,h,w ------- 0 00000000 *1 001870 h sacsr7[r/w] b,h,w 0 ---- 000 00000000 stmr7[r] b,h,w 00000000 00000000 001874 h stmcr7[r/w] b,h,w 00000000 00000000 D /(scscr7/sfur7)[r/w] b,h,w -------- -------- *3 *4 001878 h D /(scstr37)/ (lamsr7) [r/w] b,h,w -------- *3 D /(scstr27)/ (lamcr7) [r/w] b,h,w -------- *3 D /(scstr17)/ (sflr17) [r/w] b,h,w -------- *3 D /(scstr07)/ (sflr07) [r/w] b,h,w -------- *3 00187c h D D /(scsfr27) [r/w] b,h,w -------- *3 D /(scsfr17) [r/w] b,h,w -------- *3 D /(scsfr07) [ r/w] b,h,w -------- *3 001880 h D/(tbyte37)/ (lamesr7) [r/w] b,h,w -------- *3 D/(tbyte27)/ (lamert7) [r/w] b,h,w -------- *3 D/(tbyte17)/ (lamier7) [r/w] b,h,w -------- *3 tbyte07/(lamrid7) / (lamtid7) [r/w] b,h,w 00000000 001884 h bgr7[r/w] h, w 000000 00 00000000 D /(ismk7)[r/w] b,h,w -------- *2 D /(isba7)[r/w] b,h,w -------- *2 001888 h fcr17[r/w] b,h,w --- 00100 fcr07[r/w] b,h,w - 0000000 fbyte7[r/w] b,h,w 00000000 00000000 00188c h fticr7[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 90 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001890 h scr8/(ibcr8) [r/w] b,h,w 0 -- 00000 smr8[r/w] b,h,w 000 - 00 - 0 ssr8[r/w] b,h,w 0 - 000011 escr8/(ibsr8)[r/w] b,h,w 00000000 multi - uart8 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately a fter reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 001894 h D /(rdr18/(tdr18))[r/w] b, h,w -------- -------- *3 rdr08/(tdr08)[r/w] b,h,w ------- 0 00000000 *1 001898 h sacsr8[r/w] b,h,w 0 ---- 000 00000000 stmr8[r] b,h,w 00000000 00000000 00189c h stmcr8[r/w] b,h,w 00000000 00000000 D /(scscr8/sfur8)[r/w] b,h,w -------- -------- *3 *4 0018a0 h D /(scstr38)/ (lamsr8) [r/w] b,h,w -------- *3 D /(scstr28)/ (lamcr 8) [r/w] b,h,w -------- *3 D /(scstr18)/ (sflr18) [r/w] b,h,w -------- *3 D /(scstr08)/ (sflr08) [r/w] b,h,w -------- *3 0018a4 h D D /(scsfr28) [r/w] b,h,w -------- *3 D /(scsfr18) [r/w] b,h,w -------- *3 D /(scsfr08) [r/w] b,h,w -------- *3 0018a8 h D /(tbyte38)/ (lamesr8) [r/w] b,h,w -------- *3 D/(tbyte28)/ (lamert8) [r/w] b,h,w -------- *3 D/(tbyte18)/ (lamier8) [r/w] b,h,w -------- *3 tbyte08/(lamrid8) / (lamtid8) [r/w] b,h,w 00000000 0018ac h bgr8[r/w] h,w 00000000 00000000 D /(ismk8)[r/w] b,h,w - ------- *2 D /(isba8)[r/w] b,h,w -------- *2 0018b0 h fcr18[r/w] b,h,w --- 00100 fcr08[r/w] b,h,w - 0000000 fbyte8[r/w] b,h,w 00000000 00000000 0018b4 h fticr8[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 91 confidential address address offset value / register name block +0 +1 +2 +3 0018b8 h scr9/(ibcr9) [r/w] b,h,w 0 -- 00000 smr9[r/w] b,h,w 000 - 00 - 0 ssr9[r/w] b,h,w 0 - 000011 escr9/(ibsr9)[r/w] b,h,w 00000000 multi - uart9 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 0018bc h D /(rdr19/(tdr19))[r/w] b, h,w -------- -------- *3 rdr09/(tdr09)[r/w] b,h,w ------- 0 00000000 *1 0018c0 h sacsr9[r/w] b,h,w 0 ---- 0 00 00000000 stmr9[r] b,h,w 00000000 00000000 0018c4 h stmcr9[r/w] b,h,w 00000000 00000000 D /(scscr9/sfur9)[r/w] b,h,w -------- -------- *3 *4 0018c8 h D /(scstr39)/ (lamsr9) [r/w] b,h,w -------- *3 D /(scstr29)/ (lamcr9) [r/w] b,h,w -------- *3 D /(scs tr19)/ (sflr19) [r/w] b,h,w -------- *3 D /(scstr09)/ (sflr09) [r/w] b,h,w -------- *3 0018cc h D D /(scsfr29) [r/w] b,h,w -------- *3 D /(scsfr19) [r/w] b,h,w -------- *3 D /(scsfr09) [r/w] b,h,w -------- *3 0018d0 h D/(tbyte39)/ (lamesr9) [r/w] b,h,w -------- *3 D/(tbyte29)/ (lamert9) [r/w] b,h,w -------- *3 D/(tbyte19)/ (lamier9) [r/w] b,h,w -------- *3 tbyte09/(lamrid9) / (lamtid9) [r/w] b,h,w 00000000 0018d4 h bgr9[r/w] h, w 00000000 00000000 D /(ismk9)[r/w] b,h,w -------- *2 D /(isba9)[r/w] b,h,w -------- *2 0018d8 h fcr19[r/w] b,h,w --- 00100 fcr09[r/w] b,h,w - 0000000 fbyte9[r/w] b,h,w 00000000 00000000 0018dc h fticr9[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 92 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0018e0 h scr10/(ibcr10) [r/w] b,h,w 0 -- 00000 smr10[r/w] b,h,w 000 - 00 - 0 ssr10[r/w] b,h,w 0 - 000011 escr10/(ibsr10) [r/w] b,h,w 00000000 multi - uart10 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set imme diately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 0018e4 h D /(rdr110/(tdr110))[r/w] b, h,w -------- -------- *3 rdr010/(tdr010)[r/w] b,h,w ------- 0 00000000 *1 0018e8 h sacsr10[r/w] b,h,w 0 ---- 000 00000000 stmr10[r ] b,h,w 00000000 00000000 0018ec h stmcr10[r/w] b,h,w 00000000 00000000 D /(scscr10/sfur10)[r/w] b,h,w -------- -------- *3 *4 0018f0 h D /(scstr310)/ (lamsr10) [r/w] b,h,w -------- *3 D /(scstr210)/ (lamcr10) [r/w] b,h,w -------- *3 D /(scstr110)/ (sfl r110)[r/w] b,h,w -------- *3 D /(scstr010)/ (sflr010)[r/w] b,h,w -------- *3 0018f4 h D D /(scsfr210) [r/w] b,h,w -------- *3 D /(scsfr110) [r/w] b,h,w -------- *3 D /(scsfr010) [r/w] b,h,w -------- *3 0018f8 h D/(tbyte310)/ (lamesr10) [r/w] b,h,w ---- ---- *3 D/(tbyte210)/ (lamert10) [r/w] b,h,w -------- *3 D/(tbyte110)/ (lamier10) [r/w] b,h,w -------- *3 tbyte010/(lamrid 10)/(lamtid10) [r/w] b,h,w 00000000 0018fc h bgr10[r/w] h, w 00000000 00000000 D /(ismk10)[r/w] b,h,w -------- *2 D /(isba10)[r/w] b, h,w -------- *2 001900 h fcr110[r/w] b,h,w --- 00100 fcr010[r/w] b,h,w - 0000000 fbyte10[r/w] b,h,w 00000000 00000000 001904 h fticr10[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 93 confidential address address offset value / register name block +0 +1 +2 +3 001908 h scr11/(ibcr11) [r/w] b,h,w 0 -- 00000 smr11[r/w] b ,h,w 000 - 00 - 0 ssr11[r/w] b,h,w 0 - 000011 escr11/(ibsr11) [r/w] b,h,w 00000000 multi - uart11 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset. *3 : reserved because csio mode is not set immediately after reset. *4 : reserved because lin2.1 mode is not set immediately after reset. 00190c h D /(rdr111/(tdr111))[r/w] b, h,w -------- -------- *3 rdr011/(tdr011)[r/w] b,h,w ------- 0 00000000 *1 001910 h sacsr11[r/w] b,h,w 0 ---- 000 00000000 stmr11[r] b,h,w 00000000 00000000 001914 h stmcr11[r/w] b,h,w 00000000 00000000 D /(scscr11/sfur11)[r/w] b,h,w -------- -------- *3 *4 001918 h D /(scstr311)/ (lamsr11) [r/w] b,h,w -------- *3 D /(scstr211)/ (lamcr11) [r/w] b,h,w -------- *3 D /(scstr1 11)/ (sflr111)[r/w] b,h,w -------- *3 D /(scstr011)/ (sflr011)[r/w] b,h,w -------- *3 00191c h D D /(scsfr211) [r/w] b,h,w -------- *3 D /(scsfr111) [r/w] b,h,w -------- *3 D /(scsfr011) [r/w] b,h,w -------- *3 001920 h D/(tbyte311)/ (lamesr11) [r/w] b, h,w -------- *3 D/(tbyte211)/ (lamert11) [r/w] b,h,w -------- *3 D/(tbyte111)/ (lamier11) [r/w] b,h,w -------- *3 tbyte011/(lamrid 11)/(lamtid11) [r/w] b,h,w 00000000 001924 h bgr11[r/w] h, w 00000000 00000000 D /(ismk11)[r/w] b,h,w -------- *2 D /(isba11 )[r/w] b,h,w -------- *2 001928 h fcr111[r/w] b,h,w --- 00100 fcr011[r/w] b,h,w - 0000000 fbyte11[r/w] b,h,w 00000000 00000000 00192c h fticr11[r/w] b,h,w 00000000 00000000 D D 001930 h to 0019d8 h D D D D reserved 0019dc h D gatec0 [r/w] b,h,w ------ 0 0 D gatec2 [r/w] b,h,w ------ 00 ppg gate control 0019e0 h D gatec4 [r/w] b,h,w ------ 00 D D 0019e4 h D D D D reserved 0019e8 h gtrs0 [r/w] b,h,w - 0000000 - 0000000 gtrs1 [r/w] b,h,w - 0000000 - 0000000 ppg controller 0019ec h gtrs2 [r/w] b,h,w - 0000000 - 00 00000 gtrs3 [r/w] b,h,w - 0000000 - 0000000 0019f0 h gtrs4 [r/w] b,h,w - 0000000 - 0000000 gtrs5 [r/w] b,h,w - 0000000 - 0000000 0019f4 h gtrs6 [r/w] b,h,w - 0000000 - 0000000 gtrs7 [r/w] b,h,w - 0000000 - 0000000 d a t a s h e e t 94 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 0019f8 h gtrs8 [r/w] b,h,w - 0000000 - 0000000 gtrs 9 [r/w] b,h,w - 0000000 - 0000000 ppg controller 0019fc h gtrs10 [r/w] b,h,w - 0000000 - 0000000 gtrs11 [r/w] b,h,w - 0000000 - 0000000 001a00 h gtrs12 [r/w] b,h,w - 0000000 - 0000000 gtrs13 [r/w] b,h,w - 0000000 - 0000000 001a04 h gtrs14 [r/w] b,h,w - 0000000 - 000 0000 gtrs15 [r/w] b,h,w - 0000000 - 0000000 001a08 h gtrs16 [r/w] b,h,w - 0000000 - 0000000 gtrs17 [r/w] b,h,w - 0000000 - 0000000 001a0c h gtrs18 [r/w] b,h,w - 0000000 - 0000000 gtrs19 [r/w] b,h,w - 0000000 - 0000000 001a10 h gtrs20 [r/w] b,h,w - 0000000 - 0000000 gtrs21 [r/w] b,h,w - 0000000 - 0000000 001a14 h gtrs22 [r/w] b,h,w - 0000000 - 0000000 gtrs23 [r/w] b,h,w - 0000000 - 0000000 001a18 h to 001a2c h D D D D reserved 001a30 h D D D D reserved 001a34 h D D D D 001a38 h gtren0 [r/w] h,w 00000000 00000000 gtren1 [r/w] h,w 00000000 00000000 ppg controller 001a3c h gtren2 [r/w] h,w 00000000 00000000 D D 001a40 h pcn0 [r/w] b,h,w 00000000 000000 - 0 pcsr0 [w] h,w xxxxxxxx xxxxxxxx ppg0 * for communication 001a44 h pdut0 [w] h,w xxxxxxxx xxxxxxxx ptmr0 [r] h,w 11111111 11111111 001a48 h pcn200 [r/w] b,h,w -- 000000 ----- 110 psdr0 [r/w] h,w 00000000 00000000 001a4c h ptpc0 [r/w] h,w 00000000 00000000 pcmdwd0 [r/w] b,h,w -------- ---- 0000 001a50 h phcsr0 [w] h,w xxxxxxxx xxxxxxxx plcsr0 [w] h,w xxxxxxxx xxxxxxxx 001a5 4 h phdut0 [w] h,w xxxxxxxx xxxxxxxx pldut0 [w] h,w xxxxxxxx xxxxxxxx 001a58 h pcmddt0 [r/w] h,w 00000000 00000000 D D 001a5c h pcn1 [r/w] b,h,w 00000000 000000 - 0 pcsr1 [w] h,w xxxxxxxx xxxxxxxx ppg1 * for communication 001a60 h pdut1 [w] h,w xxxxxxxx xxx xxxxx ptmr1 [r] h,w 11111111 11111111 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 95 confidential address address offset value / register name block +0 +1 +2 +3 001a64 h pcn201 [r/w] b,h,w -- 000000 ----- 110 psdr1 [r/w] h,w 00000000 00000000 ppg1 * for communication 001a68 h ptpc1 [r/w] h,w 00000000 00000000 pcmdwd1 [r/w] b,h,w -------- ---- 0000 001a6c h phcsr1 [w] h,w xxxxxx xx xxxxxxxx plcsr1 [w] h,w xxxxxxxx xxxxxxxx 001a70 h phdut1 [w] h,w xxxxxxxx xxxxxxxx pldut1 [w] h,w xxxxxxxx xxxxxxxx 001a74 h pcmddt1 [r/w] h,w 00000000 00000000 D D 001a78 h pcn2 [r/w] b,h,w 00000000 000000 - 0 pcsr2 [w] h,w xxxxxxxx xxxxxxxx ppg2 * f or communication 001a7c h pdut2 [w] h,w xxxxxxxx xxxxxxxx ptmr2 [r] h,w 11111111 11111111 001a80 h pcn202 [r/w] b,h,w -- 000000 ----- 110 psdr2 [r/w] h,w 00000000 00000000 001a84 h ptpc2 [r/w] h,w 00000000 00000000 pcmdwd2 [r/w] b,h,w -------- ---- 0000 0 01a88 h phcsr2 [w] h,w xxxxxxxx xxxxxxxx plcsr2 [w] h,w xxxxxxxx xxxxxxxx 001a8c h phdut2 [w] h,w xxxxxxxx xxxxxxxx pldut2 [w] h,w xxxxxxxx xxxxxxxx 001a90 h pcmddt2 [r/w] h,w 00000000 00000000 D D 001a94 h pcn3 [r/w] b,h,w 00000000 000000 - 0 pcsr3 [w] h, w xxxxxxxx xxxxxxxx ppg3 * for communication 001a98 h pdut3 [w] h,w xxxxxxxx xxxxxxxx ptmr3 [r] h,w 11111111 11111111 001a9c h pcn203 [r/w] b,h,w -- 000000 ----- 110 psdr3 [r/w] h,w 00000000 00000000 001aa0 h ptpc3 [r/w] h,w 00000000 00000000 pcmdwd3 [r/w] b,h,w -------- ---- 0000 001aa4 h phcsr3 [w] h,w xxxxxxxx xxxxxxxx plcsr3 [w] h,w xxxxxxxx xxxxxxxx 001aa8 h phdut3 [w] h,w xxxxxxxx xxxxxxxx pldut3 [w] h,w xxxxxxxx xxxxxxxx 001aac h pcmddt3 [r/w] h,w 00000000 00000000 D D 001ab0 h pcn4 [r/w] b,h,w 00 000000 000000 - 0 pcsr4 [w] h,w xxxxxxxx xxxxxxxx ppg4 001ab4 h pdut4 [w] h,w xxxxxxxx xxxxxxxx ptmr4 [r] h,w 11111111 11111111 001ab8 h pcn204 [r/w] b,h,w -- 000000 ----- 110 psdr4 [r/w] h,w 00000000 00000000 d a t a s h e e t 96 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001abc h ptpc4 [r/w] h,w 00000000 00000000 D D p pg4 001ac0 h pcn5 [r/w] b,h,w 00000000 000000 - 0 pcsr5 [w] h,w xxxxxxxx xxxxxxxx ppg5 001ac4 h pdut5 [w] h,w xxxxxxxx xxxxxxxx ptmr5 [r] h,w 11111111 11111111 001ac8 h pcn205 [r/w] b,h,w -- 000000 ----- 110 psdr5 [r/w] h,w 00000000 00000000 001acc h ptpc5 [ r/w] h,w 00000000 00000000 D D 001ad0 h pcn6 [r/w] b,h,w 00000000 000000 - 0 pcsr6 [w] h,w xxxxxxxx xxxxxxxx ppg6 001ad4 h pdut6 [w] h,w xxxxxxxx xxxxxxxx ptmr6 [r] h,w 11111111 11111111 001ad8 h pcn206 [r/w] b,h,w -- 000000 ----- 110 psdr6 [r/w] h,w 0000000 0 00000000 001adc h ptpc6 [r/w] h,w 00000000 00000000 D D 001ae0 h pcn7 [r/w] b,h,w 00000000 000000 - 0 pcsr7 [w] h,w xxxxxxxx xxxxxxxx ppg7 001ae4 h pdut7 [w] h,w xxxxxxxx xxxxxxxx ptmr7 [r] h,w 11111111 11111111 001ae8 h pcn207 [r/w] b,h,w -- 000000 ---- - 110 psdr7 [r/w] h,w 00000000 00000000 001aec h ptpc7 [r/w] h,w 00000000 00000000 D D 001af0 h pcn8 [r/w] b,h,w 00000000 000000 - 0 pcsr8 [w] h,w xxxxxxxx xxxxxxxx ppg8 001af4 h pdut8 [w] h,w xxxxxxxx xxxxxxxx ptmr8 [r] h,w 11111111 11111111 001af8 h pcn2 08 [r/w] b,h,w -- 000000 ----- 110 psdr8 [r/w] h,w 00000000 00000000 001afc h ptpc8 [r/w] h,w 00000000 00000000 D D 001b00 h pcn9 [r/w] b,h,w 00000000 000000 - 0 pcsr9 [w] h,w xxxxxxxx xxxxxxxx ppg9 001b04 h pdut9 [w] h,w xxxxxxxx xxxxxxxx ptmr9 [r] h,w 1111 1111 11111111 001b08 h pcn209 [r/w] b,h,w -- 000000 ----- 110 psdr9 [r/w] h,w 00000000 00000000 001b0c h ptpc9 [r/w] h,w 00000000 00000000 D D 001b10 h pcn10 [r/w] b,h,w 00000000 000000 - 0 pcsr10 [w] h,w xxxxxxxx xxxxxxxx ppg10 001b14 h pdut10 [w] h,w xxxx xxxx xxxxxxxx ptmr10 [r] h,w 11111111 11111111 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 97 confidential address address offset value / register name block +0 +1 +2 +3 001b18 h pcn210 [r/w] b,h,w -- 000000 ----- 110 psdr10 [r/w] h,w 00000000 00000000 ppg10 001b1c h ptpc10 [r/w] h,w 00000000 00000000 D D 001b20 h pcn11 [r/w] b,h,w 00000000 000000 - 0 pcsr11 [w] h,w xxxxxxxx xxx xxxxx ppg11 001b24 h pdut11 [w] h,w xxxxxxxx xxxxxxxx ptmr11 [r] h,w 11111111 11111111 001b28 h pcn211 [r/w] b,h,w -- 000000 ----- 110 psdr11 [r/w] h,w 00000000 00000000 001b2c h ptpc11 [r/w] h,w 00000000 00000000 D D 001b30 h pcn12 [r/w] b,h,w 00000000 0 00000 - 0 pcsr12 [w] h,w xxxxxxxx xxxxxxxx ppg12 001b34 h pdut12 [w] h,w xxxxxxxx xxxxxxxx ptmr12 [r] h,w 11111111 11111111 001b38 h pcn212 [r/w] b,h,w -- 000000 ----- 110 psdr12 [r/w] h,w 00000000 00000000 001b3c h ptpc12 [r/w] h,w 00000000 00000000 D D 0 01b40 h pcn13 [r/w] b,h,w 00000000 000000 - 0 pcsr13 [w] h,w xxxxxxxx xxxxxxxx ppg13 001b44 h pdut13 [w] h,w xxxxxxxx xxxxxxxx ptmr13 [r] h,w 11111111 11111111 001b48 h pcn213 [r/w] b,h,w -- 000000 ----- 110 psdr13 [r/w] h,w 00000000 00000000 001b4c h ptpc13 [r/w] h,w 00000000 00000000 D D 001b50 h pcn14 [r/w] b,h,w 00000000 000000 - 0 pcsr14 [w] h,w xxxxxxxx xxxxxxxx ppg14 001b54 h pdut14 [w] h,w xxxxxxxx xxxxxxxx ptmr14 [r] h,w 11111111 11111111 001b58 h pcn214 [r/w] b,h,w -- 000000 ----- 110 psdr14 [r/w] h,w 00000000 00000000 001b5c h ptpc14 [r/w] h,w 00000000 00000000 D D 001b60 h pcn15 [r/w] b,h,w 00000000 000000 - 0 pcsr15 [w] h,w xxxxxxxx xxxxxxxx ppg15 001b64 h pdut15 [w] h,w xxxxxxxx xxxxxxxx ptmr15 [r] h,w 11111111 11111111 001b68 h pcn215 [r/w] b,h,w -- 000000 ----- 110 psdr15 [r/w] h,w 00000000 00000000 001b6c h ptpc15 [r/w] h,w 00000000 00000000 D D 001b70 h pcn16 [r/w] b,h,w 00000000 000000 - 0 pcsr16 [w] h,w xxxxxxxx xxxxxxxx ppg16 d a t a s h e e t 98 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001b74 h pdut16 [w] h,w xxxxxxxx xxxxxxxx ptmr16 [r] h,w 11111111 111 11111 ppg16 001b78 h pcn216 [r/w] b,h,w -- 000000 ----- 110 psdr16 [r/w] h,w 00000000 00000000 001b7c h ptpc16 [r/w] h,w 00000000 00000000 D D 001b80 h pcn17 [r/w] b,h,w 00000000 000000 - 0 pcsr17 [w] h,w xxxxxxxx xxxxxxxx ppg17 001b84 h pdut17 [w] h,w xxxxx xxx xxxxxxxx ptmr17 [r] h,w 11111111 11111111 001b88 h pcn217 [r/w] b,h,w -- 000000 ----- 110 psdr17 [r/w] h,w 00000000 00000000 001b8c h ptpc17 [r/w] h,w 00000000 00000000 D D 001b90 h pcn18 [r/w] b,h,w 00000000 000000 - 0 pcsr18 [w] h,w xxxxxxxx xxxxxxxx ppg18 001b94 h pdut18 [w] h,w xxxxxxxx xxxxxxxx ptmr18 [r] h,w 11111111 11111111 001b98 h pcn218 [r/w] b,h,w -- 000000 ----- 110 psdr18 [r/w] h,w 00000000 00000000 001b9c h ptpc18 [r/w] h,w 00000000 00000000 D D 001ba0 h pcn19 [r/w] b,h,w 00000000 000000 - 0 pcsr19 [w] h,w xxxxxxxx xxxxxxxx ppg19 001ba4 h pdut19 [w] h,w xxxxxxxx xxxxxxxx ptmr19 [r] h,w 11111111 11111111 001ba8 h pcn219 [r/w] b,h,w -- 000000 ----- 110 psdr19 [r/w] h,w 00000000 00000000 001bac h ptpc19 [r/w] h,w 00000000 00000000 D D 001bb0 h pcn20 [r/w] b,h,w 00000000 000000 - 0 pcsr20 [w] h,w xxxxxxxx xxxxxxxx ppg20 001bb4 h pdut20 [w] h,w xxxxxxxx xxxxxxxx ptmr20 [r] h,w 11111111 11111111 001bb8 h pcn220 [r/w] b,h,w -- 000000 ----- 110 psdr20 [r/w] h,w 00000000 00000000 001bbc h ptpc20 [r/w] h,w 00000000 00000000 D D 001bc0 h pcn21 [r/w] b,h,w 00000000 000000 - 0 pcsr21 [w] h,w xxxxxxxx xxxxxxxx ppg21 001bc4 h pdut21 [w] h,w xxxxxxxx xxxxxxxx ptmr21 [r] h,w 11111111 11111111 001bc8 h pcn221 [r/w] b,h,w -- 000000 ----- 110 psdr21 [r/w] h,w 000000 00 00000000 001bcc h ptpc21 [r/w] h,w 00000000 00000000 D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 99 confidential address address offset value / register name block +0 +1 +2 +3 001bd0 h pcn22 [r/w] b,h,w 00000000 000000 - 0 pcsr22 [w] h,w xxxxxxxx xxxxxxxx ppg22 001bd4 h pdut22 [w] h,w xxxxxxxx xxxxxxxx ptmr22 [r] h,w 11111111 11111111 001bd8 h pcn222 [r/w] b,h,w -- 0000 00 ----- 110 psdr22 [r/w] h,w 00000000 00000000 001bdc h ptpc22 [r/w] h,w 00000000 00000000 D D 001be0 h pcn23 [r/w] b,h,w 00000000 000000 - 0 pcsr23 [w] h,w xxxxxxxx xxxxxxxx ppg23 001be4 h pdut23 [w] h,w xxxxxxxx xxxxxxxx ptmr23 [r] h,w 11111111 11111111 001be8 h pcn223 [r/w] b,h,w -- 000000 ----- 110 psdr23 [r/w] h,w 00000000 00000000 001bec h ptpc23 [r/w] h,w 00000000 00000000 D D 001bf0 h pcn24 [r/w] b,h,w 00000000 000000 - 0 pcsr24 [w] h,w xxxxxxxx xxxxxxxx ppg24 001bf4 h pdut24 [w] h,w xxxxxxxx xxxxxxx x ptmr24 [r] h,w 11111111 11111111 001bf8 h pcn224 [r/w] b,h,w -- 000000 ----- 110 psdr24 [r/w] h,w 00000000 00000000 001bfc h ptpc24 [r/w] h,w 00000000 00000000 D D 001c00 h pcn25 [r/w] b,h,w 00000000 000000 - 0 pcsr25 [w] h,w xxxxxxxx xxxxxxxx ppg25 001c 04 h pdut25 [w] h,w xxxxxxxx xxxxxxxx ptmr25 [r] h,w 11111111 11111111 001c08 h pcn225 [r/w] b,h,w -- 000000 ----- 110 psdr25 [r/w] h,w 00000000 00000000 001c0c h ptpc25 [r/w] h,w 00000000 00000000 D D 001c10 h pcn26 [r/w] b,h,w 00000000 000000 - 0 pcsr26 [w ] h,w xxxxxxxx xxxxxxxx ppg26 001c14 h pdut26 [w] h,w xxxxxxxx xxxxxxxx ptmr26 [r] h,w 11111111 11111111 001c18 h pcn226 [r/w] b,h,w -- 000000 ----- 110 psdr26 [r/w] h,w 00000000 00000000 001c1c h ptpc26 [r/w] h,w 00000000 00000000 D D 001c20 h pcn27 [r/w ] b,h,w 00000000 000000 - 0 pcsr27 [w] h,w xxxxxxxx xxxxxxxx ppg27 001c24 h pdut27 [w] h,w xxxxxxxx xxxxxxxx ptmr27 [r] h,w 11111111 11111111 001c28 h pcn227 [r/w] b,h,w -- 000000 ----- 110 psdr27 [r/w] h,w 00000000 00000000 001c2c h ptpc27 [r/w] h,w 0000000 0 00000000 D D d a t a s h e e t 100 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001c30 h pcn28 [r/w] b,h,w 00000000 000000 - 0 pcsr28 [w] h,w xxxxxxxx xxxxxxxx ppg28 001c34 h pdut28 [w] h,w xxxxxxxx xxxxxxxx ptmr28 [r] h,w 11111111 11111111 001c38 h pcn228 [r/w] b,h,w -- 000000 ----- 110 psdr28 [r/w] h,w 00000000 00000000 001c3c h ptpc28 [r/w] h,w 00000000 00000000 D D 001c40 h pcn29 [r/w] b,h,w 00000000 000000 - 0 pcsr29 [w] h,w xxxxxxxx xxxxxxxx ppg29 001c44 h pdut29 [w] h,w xxxxxxxx xxxxxxxx ptmr29 [r] h,w 11111111 11111111 001c48 h pcn229 [r/w] b,h,w -- 000000 ----- 110 psdr29 [r/w] h,w 00000000 00000000 001c4c h ptpc29 [r/w] h,w 00000000 00000000 D D 001c50 h pcn30 [r/w] b,h,w 00000000 000000 - 0 pcsr30 [w] h,w xxxxxxxx xxxxxxxx ppg30 001c54 h pdut30 [w] h,w xxxxxxxx xxxxxxxx ptmr30 [r] h,w 11111111 11111111 001c58 h p cn230 [r/w] b,h,w -- 000000 ----- 110 psdr30 [r/w] h,w 00000000 00000000 001c5c h ptpc30 [r/w] h,w 00000000 00000000 D D 001c60 h pcn31 [r/w] b,h,w 00000000 000000 - 0 pcsr31 [w] h,w xxxxxxxx xxxxxxxx ppg31 001c64 h pdut31 [w] h,w xxxxxxxx xxxxxxxx ptmr31 [r ] h,w 11111111 11111111 001c68 h pcn231 [r/w] b,h,w -- 000000 ----- 110 psdr31 [r/w] h,w 00000000 00000000 001c6c h ptpc31 [r/w] h,w 00000000 00000000 D D 001c70 h pcn32 [r/w] b,h,w 00000000 000000 - 0 pcsr32 [w] h,w xxxxxxxx xxxxxxxx ppg32 001c74 h pdut32 [w] h,w xxxxxxxx xxxxxxxx ptmr32 [r] h,w 11111111 11111111 001c78 h pcn232 [r/w] b,h,w -- 000000 ----- 110 psdr32 [r/w] h,w 00000000 00000000 001c7c h ptpc32 [r/w] h,w 00000000 00000000 D D 001c80 h pcn33 [r/w] b,h,w 00000000 000000 - 0 pcsr33 [w] h,w xxxxx xxx xxxxxxxx ppg33 001c84 h pdut33 [w] h,w xxxxxxxx xxxxxxxx ptmr33 [r] h,w 11111111 11111111 001c88 h pcn233 [r/w] b,h,w -- 000000 ----- 110 psdr33 [r/w] h,w 00000000 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 101 confidential address address offset value / register name block +0 +1 +2 +3 001c8c h ptpc33 [r/w] h,w 00000000 00000000 D D ppg33 001c90 h pcn34 [r/w] b,h, w 00000000 000000 - 0 pcsr34 [w] h,w xxxxxxxx xxxxxxxx ppg34 001c94 h pdut34 [w] h,w xxxxxxxx xxxxxxxx ptmr34 [r] h,w 11111111 11111111 001c98 h pcn234 [r/w] b,h,w -- 000000 ----- 110 psdr34 [r/w] h,w 00000000 00000000 001c9c h ptpc34 [r/w] h,w 00000000 0000 0000 D D 001ca0 h pcn35 [r/w] b,h,w 00000000 000000 - 0 pcsr35 [w] h,w xxxxxxxx xxxxxxxx ppg35 001ca4 h pdut35 [w] h,w xxxxxxxx xxxxxxxx ptmr35 [r] h,w 11111111 11111111 001ca8 h pcn235 [r/w] b,h,w -- 000000 ----- 110 psdr35 [r/w] h,w 00000000 00000000 001 cac h ptpc35 [r/w] h,w 00000000 00000000 D D 001cb0 h pcn36 [r/w] b,h,w 00000000 000000 - 0 pcsr36 [w] h,w xxxxxxxx xxxxxxxx ppg36 001cb4 h pdut36 [w] h,w xxxxxxxx xxxxxxxx ptmr36 [r] h,w 11111111 11111111 001cb8 h pcn236 [r/w] b,h,w -- 000000 ----- 110 psdr3 6 [r/w] h,w 00000000 00000000 001cbc h ptpc36 [r/w] h,w 00000000 00000000 D D 001cc0 h pcn37 [r/w] b,h,w 00000000 000000 - 0 pcsr37 [w] h,w xxxxxxxx xxxxxxxx ppg37 001cc4 h pdut37 [w] h,w xxxxxxxx xxxxxxxx ptmr37 [r] h,w 11111111 11111111 001cc8 h pcn237 [r/w] b,h,w -- 000000 ----- 110 psdr37 [r/w] h,w 00000000 00000000 001ccc h ptpc37 [r/w] h,w 00000000 00000000 D D 001cd0 h pcn38 [r/w] b,h,w 00000000 000000 - 0 pcsr38 [w] h,w xxxxxxxx xxxxxxxx ppg38 001cd4 h pdut38 [w] h,w xxxxxxxx xxxxxxxx ptmr38 [r] h,w 11111111 11111111 001cd8 h pcn238 [r/w] b,h,w -- 000000 ----- 110 psdr38 [r/w] h,w 00000000 00000000 001cdc h ptpc38 [r/w] h,w 00000000 00000000 D D 001ce0 h pcn39 [r/w] b,h,w 00000000 000000 - 0 pcsr39 [w] h,w xxxxxxxx xxxxxxxx ppg39 001ce4 h pdut39 [w] h, w xxxxxxxx xxxxxxxx ptmr39 [r] h,w 11111111 11111111 d a t a s h e e t 102 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 001ce8 h pcn239 [r/w] b,h,w -- 000000 ----- 110 psdr39 [r/w] h,w 00000000 00000000 ppg39 001cec h ptpc39 [r/w] h,w 00000000 00000000 D D 001cf0 h pcn40 [r/w] b,h,w 00000000 000000 - 0 pcsr40 [w] h,w xxxxxx xx xxxxxxxx ppg40 001cf4 h pdut40 [w] h,w xxxxxxxx xxxxxxxx ptmr40 [r] h,w 11111111 11111111 001cf8 h pcn240 [r/w] b,h,w -- 000000 ----- 110 psdr40 [r/w] h,w 00000000 00000000 001cfc h ptpc40 [r/w] h,w 00000000 00000000 D D 001d00 h pcn41 [r/w] b,h,w 0000 0000 000000 - 0 pcsr41 [w] h,w xxxxxxxx xxxxxxxx ppg41 001d04 h pdut41 [w] h,w xxxxxxxx xxxxxxxx ptmr41 [r] h,w 11111111 11111111 001d08 h pcn241 [r/w] b,h,w -- 000000 ----- 110 psdr41 [r/w] h,w 00000000 00000000 001d0c h ptpc41 [r/w] h,w 00000000 00000000 D D 001d10 h pcn42 [r/w] b,h,w 00000000 000000 - 0 pcsr42 [w] h,w xxxxxxxx xxxxxxxx ppg42 001d14 h pdut42 [w] h,w xxxxxxxx xxxxxxxx ptmr42 [r] h,w 11111111 11111111 001d18 h pcn242 [r/w] b,h,w -- 000000 ----- 110 psdr42 [r/w] h,w 00000000 00000000 001d1c h p tpc42 [r/w] h,w 00000000 00000000 D D 001d20 h pcn43 [r/w] b,h,w 00000000 000000 - 0 pcsr43 [w] h,w xxxxxxxx xxxxxxxx ppg43 001d24 h pdut43 [w] h,w xxxxxxxx xxxxxxxx ptmr43 [r] h,w 11111111 11111111 001d28 h pcn243 [r/w] b,h,w -- 000000 ----- 110 psdr43 [r/w ] h,w 00000000 00000000 001d2c h ptpc43 [r/w] h,w 00000000 00000000 D D 001d30 h pcn44 [r/w] b,h,w 00000000 000000 - 0 pcsr44 [w] h,w xxxxxxxx xxxxxxxx ppg44 001d34 h pdut44 [w] h,w xxxxxxxx xxxxxxxx ptmr44 [r] h,w 11111111 11111111 001d38 h pcn244 [r/w] b,h,w -- 000000 ----- 110 psdr44 [r/w] h,w 00000000 00000000 001d3c h ptpc44 [r/w] h,w 00000000 00000000 D D 001d40 h pcn45 [r/w] b,h,w 00000000 000000 - 0 pcsr45 [w] h,w xxxxxxxx xxxxxxxx ppg45 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 103 confidential address address offset value / register name block +0 +1 +2 +3 001d44 h pdut45 [w] h,w xxxxxxxx xxxxxxxx ptmr45 [r] h,w 111111 11 11111111 ppg45 001d48 h pcn245 [r/w] b,h,w -- 000000 ----- 110 psdr45 [r/w] h,w 00000000 00000000 001d4c h ptpc45 [r/w] h,w 00000000 00000000 D D 001d50 h pcn46 [r/w] b,h,w 00000000 000000 - 0 pcsr46 [w] h,w xxxxxxxx xxxxxxxx ppg46 001d54 h pdut46 [w] h,w xxxxxxxx xxxxxxxx ptmr46 [r] h,w 11111111 11111111 001d58 h pcn246 [r/w] b,h,w -- 000000 ----- 110 psdr46 [r/w] h,w 00000000 00000000 001d5c h ptpc46 [r/w] h,w 00000000 00000000 D D 001d60 h pcn47 [r/w] b,h,w 00000000 000000 - 0 pcsr47 [w] h,w xxxxxxxx xxx xxxxx ppg47 001d64 h pdut47 [w] h,w xxxxxxxx xxxxxxxx ptmr47 [r] h,w 11111111 11111111 001d68 h pcn247 [r/w] b,h,w -- 000000 ----- 110 psdr47 [r/w] h,w 00000000 00000000 001d6c h ptpc47 [r/w] h,w 00000000 00000000 D D 001d70 h to 001ffc h D D D D reserved 002000 h ctrlr0 [r/w] b,h,w -------- 000 - 0001 statr0 [r/w] b,h,w -------- 00000000 can0 (128msb) 002004 h errcnt0 [r] b,h,w 00000000 00000000 btr0 [r/w] b,h,w - 0100011 00000001 002008 h intr0 [r] b,h,w 00000000 00000000 testr0 [r/w] b,h,w -------- x00000 -- 00200c h brper0 [r/w] b,h,w -------- ---- 0000 D D 002010 h if1creq0 [r/w] b,h,w 0 ------- 00000001 if1cmsk0 [r/w] b,h,w -------- 00000000 002014 h if1msk20 [r/w] b,h,w 11 - 11111 11111111 if1msk10 [r/w] b,h,w 11111111 11111111 002018 h if1arb20 [r/w] b ,h,w 00000000 00000000 if1arb10 [r/w] b,h,w 00000000 00000000 00201c h if1mctr0 [r/w] b,h,w 00000000 0 --- 0000 D D 002020 h if1dta10 [r/w] b,h,w 00000000 00000000 if1dta20 [r/w] b,h,w 00000000 00000000 002024 h if1dtb10 [r/w] b,h,w 00000000 00000000 if1d tb20 [r/w] b,h,w 00000000 00000000 d a t a s h e e t 104 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 002028 h D D D D can0 (128msb) 00202c h D D D D 002030 h , 002034 h reserved(if1 data mirror) 002038 h D D D D 00203c h D D D D 002040 h if2creq0 [r/w] b,h,w 0 ------- 00000001 if2cmsk0 [r/w] b,h,w -------- 00000000 002044 h if2msk20 [r/w] b,h,w 11 - 11111 11111111 if2msk10 [r/w] b,h,w 11111111 11111111 002048 h if2arb20 [r/w] b,h,w 00000000 00000000 if2arb10 [r/w] b,h,w 00000000 00000000 00204c h if2mctr0 [r/w] b,h,w 00000000 0 --- 0000 D D 002050 h if2dta10 [r/w] b,h, w 00000000 00000000 if2dta20 [r/w] b,h,w 00000000 00000000 002054 h if2dtb10 [r/w] b,h,w 00000000 00000000 if2dtb20 [r/w] b,h,w 00000000 00000000 002058 h D D D D 00205c h D D D D 002060 h , 002064 h reserved(if2 data mirror) 002068 h to 00207c h D 0 02080 h treqr20 [r] b,h,w 00000000 00000000 treqr10 [r] b,h,w 00000000 00000000 002084 h treqr40 [r] b,h,w 00000000 00000000 treqr30 [r] b,h,w 00000000 00000000 002088 h treqr60 [r] b,h,w 00000000 00000000 treqr50 [r] b,h,w 00000000 00000000 00208c h tre qr80 [r] b,h,w 00000000 00000000 treqr70 [r] b,h,w 00000000 00000000 002090 h newdt20 [r] b,h,w 00000000 00000000 newdt10 [r] b,h,w 00000000 00000000 002094 h newdt40 [r] b,h,w 00000000 00000000 newdt30 [r] b,h,w 00000000 00000000 002098 h newdt60 [r] b ,h,w 00000000 00000000 newdt50 [r] b,h,w 00000000 00000000 00209c h newdt80 [r] b,h,w 00000000 00000000 newdt70 [r] b,h,w 00000000 00000000 0020a0 h intpnd20 [r] b,h,w 00000000 00000000 intpnd10 [r] b,h,w 00000000 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 105 confidential address address offset value / register name block +0 +1 +2 +3 0020a4 h intpnd40 [r] b,h,w 00 000000 00000000 intpnd30 [r] b,h,w 00000000 00000000 can0 (128msb) 0020a8 h intpnd60 [r] b,h,w 00000000 00000000 intpnd50 [r] b,h,w 00000000 00000000 0020ac h intpnd80 [r] b,h,w 00000000 00000000 intpnd70 [r] b,h,w 00000000 00000000 0020b0 h msgval20 [r] b,h,w 00000000 00000000 msgval10 [r] b,h,w 00000000 00000000 0020b4 h msgval40 [r] b,h,w 00000000 00000000 msgval30 [r] b,h,w 00000000 00000000 0020b8 h msgval60 [r] b,h,w 00000000 00000000 msgval50 [r] b,h,w 00000000 00000000 0020bc h msgval80 [r] b,h ,w 00000000 00000000 msgval70 [r] b,h,w 00000000 00000000 0020c0 h to 0020fc h D 002100 h ctrlr1 [r/w] b,h,w -------- 000 - 0001 statr1 [r/w] b,h,w -------- 00000000 can1 (64msb) 002104 h errcnt1 [r] b,h,w 00000000 00000000 btr1 [r/w] b,h,w - 0100011 000000 01 002108 h intr1 [r] b,h,w 00000000 00000000 testr1 [r/w] b,h,w -------- x00000 -- 00210c h brper1 [r/w] b,h,w -------- ---- 0000 D D 002110 h if1creq1 [r/w] b,h,w 0 ------- 00000001 if1cmsk1 [r/w] b,h,w -------- 00000000 002114 h if1msk21 [r/w] b,h,w 11 - 11111 11111111 if1msk11 [r/w] b,h,w 11111111 11111111 002118 h if1arb21 [r/w] b,h,w 00000000 00000000 if1arb11 [r/w] b,h,w 00000000 00000000 00211c h if1mctr1 [r/w] b,h,w 00000000 0 --- 0000 D D 002120 h if1dta11 [r/w] b,h,w 00000000 00000000 if1dta21 [r /w] b,h,w 00000000 00000000 002124 h if1dtb11 [r/w] b,h,w 00000000 00000000 if1dtb21 [r/w] b,h,w 00000000 00000000 002128 h D D D D 00212c h D D D D 002130 h , 002134 h reserved (if1 data mirror) 002138 h D D D D 00213c h D D D D d a t a s h e e t 106 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 002140 h if2creq1 [r/ w] b,h,w 0 ------- 00000001 if2cmsk1 [r/w] b,h,w -------- 00000000 can1 (64msb) 002144 h if2msk21 [r/w] b,h,w 11 - 11111 11111111 if2msk11 [r/w] b,h,w 11111111 11111111 002148 h if2arb21 [r/w] b,h,w 00000000 00000000 if2arb11 [r/w] b,h,w 00000000 00000000 00214c h if2mctr1 [r/w] b,h,w 00000000 0 --- 0000 D D 002150 h if2dta11 [r/w] b,h,w 00000000 00000000 if2dta21 [r/w] b,h,w 00000000 00000000 002154 h if2dtb11 [r/w] b,h,w 00000000 00000000 if2dtb21 [r/w] b,h,w 00000000 00000000 002158 h D D D D 00215c h D D D D 002160 h , 002164 h reserved (if2 data mirror) 002168 h to 00217c h D 002180 h treqr21 [r] b,h,w 00000000 00000000 treqr11 [r] b,h,w 00000000 00000000 002184 h treqr41 [r] b,h,w 00000000 00000000 treqr31 [r] b,h,w 00000000 00000000 002188 h D D D D 00218c h D D D D 002190 h newdt21 [r] b,h,w 00000000 00000000 newdt11 [r] b,h,w 00000000 00000000 002194 h newdt41 [r] b,h,w 00000000 00000000 newdt31 [r] b,h,w 00000000 00000000 002198 h D D D D 00219c h D D D D 0021a0 h intpnd21 [r] b,h,w 00000 000 00000000 intpnd11 [r] b,h,w 00000000 00000000 0021a4 h intpnd41 [r] b,h,w 00000000 00000000 intpnd31 [r] b,h,w 00000000 00000000 0021a8 h D D D D 0021ac h D D D D 0021b0 h msgval21 [r] b,h,w 00000000 00000000 msgval11 [r] b,h,w 00000000 00000000 0021b4 h msgval41 [r] b,h,w 00000000 00000000 msgval31 [r] b,h,w 00000000 00000000 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 107 confidential address address offset value / register name block +0 +1 +2 +3 0021b8 h D D D D can1 (64msb) 0021bc h D D D D 0021c0 h to 0021fc h D 002200 h ctrlr2 [r/w] b,h,w -------- 000 - 0001 statr2 [r/w] b,h,w -------- 00000000 can2 (64msb) 0022 04 h errcnt2 [r] b,h,w 00000000 00000000 btr2 [r/w] b,h,w - 0100011 00000001 002208 h intr2 [r] b,h,w 00000000 00000000 testr2 [r/w] b,h,w -------- x00000 -- 00220c h brper2 [r/w] b,h,w -------- ---- 0000 D 002210 h if1creq2 [r/w] b,h,w 0 ------- 00000001 if 1cmsk2 [r/w] b,h,w -------- 00000000 002214 h if1msk22 [r/w] b,h,w 11 - 11111 11111111 if1msk12 [r/w] b,h,w 11111111 11111111 002218 h if1arb22 [r/w] b,h,w 00000000 00000000 if1arb12 [r/w] b,h,w 00000000 00000000 00221c h if1mctr2 [r/w] b,h,w 00000000 0 -- - 0000 D 002220 h if1dta12 [r/w] b,h,w 00000000 00000000 if1dta22 [r/w] b,h,w 00000000 00000000 002224 h if1dtb12 [r/w] b,h,w 00000000 00000000 if1dtb22 [r/w] b,h,w 00000000 00000000 002228 h D D D D 00222c h D D D D 002230 h , 002234 h reserved (if1 dat a mirror) 002238 h D D D D 00223c h D D D D 002240 h if2creq2 [r/w] b,h,w 0 ------- 00000001 if2cmsk2 [r/w] b,h,w -------- 00000000 002244 h if2msk22 [r/w] b,h,w 11 - 11111 11111111 if2msk12 [r/w] b,h,w 11111111 11111111 002248 h if2arb22 [r/w] b,h,w 000 00000 00000000 if2arb12 [r/w] b,h,w 00000000 00000000 00224c h if2mctr2 [r/w] b,h,w 00000000 0 --- 0000 D 002250 h if2dta12 [r/w] b,h,w 00000000 00000000 if2dta22 [r/w] b,h,w 00000000 00000000 d a t a s h e e t 108 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 002254 h if2dtb12 [r/w] b,h,w 00000000 00000000 if2dtb22 [r/w] b,h,w 00000000 00000000 can2 (64msb) 002258 h D D D D 00225c h D D D D 002260 h , 002264 h reserved (if2 data mirror) 002268 h to 00227c h D 002280 h treqr22 [r] b,h,w 00000000 00000000 treqr12 [r] b,h,w 00000000 00000000 002284 h treqr42 [r] b,h,w 000 00000 00000000 treqr32 [r] b,h,w 00000000 00000000 002288 h D D D D 00228c h D D D D 002290 h newdt22 [r] b,h,w 00000000 00000000 newdt12 [r] b,h,w 00000000 00000000 002294 h newdt42 [r] b,h,w 00000000 00000000 newdt32 [r] b,h,w 00000000 00000000 002 298 h D D D D 00229c h D D D D 0022a0 h intpnd22 [r] b,h,w 00000000 00000000 intpnd12 [r] b,h,w 00000000 00000000 0022a4 h intpnd42 [r] b,h,w 00000000 00000000 intpnd32 [r] b,h,w 00000000 00000000 0022a8 h D D D D 0022ac h D D D D 0022b0 h msgval22 [r ] b,h,w 00000000 00000000 msgval12 [r] b,h,w 00000000 00000000 0022b4 h msgval42 [r] b,h,w 00000000 00000000 msgval32 [r] b,h,w 00000000 00000000 0022b8 h D D D D 0022bc h D D D D 0022c0 h to 0022fc h D 002300 h dfctlr [r/w] b,h,w - 0 ------ -------- D dfstr [r/w] b,h,w ----- 001 workflash 002304 h D D D D d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 109 confidential address address offset value / register name block +0 +1 +2 +3 002308 h flifctlr [r/w] b,h,w --- 0 -- 00 D fliffer1 [r/w] b,h,w -------- fliffer2 [r/w] b,h,w -------- flash / workflash 00230c h to 0023fc h D reserved 002400 h seearx [r] b,h,w - 0000000 00000000 dee arx [r] b,h,w - 0000000 00000000 xbs ram ecc control 002404 h eecsrx [r/w] b,h,w ---- 00 -- D efearx [r/w] b,h,w - 0000000 00000000 002408 h D efecrx [r/w] b,h,w ------- 0 00000000 00000000 00240c h to 002ffc h D reserved 003000 h seeara [r] b,h,w ----- 000 0 0000000 deeara [r] b,h,w ----- 000 00000000 backup ram ecc control 003004 h eecsra [r/w] b,h,w ---- 00 -- D efeara [r/w] b,h,w ----- 000 00000000 003008 h D efecra [r/w] b,h,w ------- 0 00000000 00000000 00300c h tear0x[r] b,h,w 000 ----- -------- - 0000000 00 000000 ram/ diagnosis xbs ram 003010 h tear1x[r] b,h,w 000 ----- -------- - 0000000 00000000 003014 h tear2x[r] b,h,w 000 ----- -------- - 0000000 00000000 003018 h taearx [r/w] b,h,w - 1111111 11111111 tasarx [r/w] b,h,w - 0000000 00000000 00301c h tfecrx [r /w] b,h,w ---- 0000 ticrx [r/w] b,h,w ---- 0000 ttcrx [r/w] b,h,w ------ 00 00001100 003020 h tsrcrx [w] b,h,w 0 ------- D D tkccrx [r/w] b,h,w 00 ---- 00 003024 h to 00302c h D reserved 003030 h tear0a[r] b,h,w 000 ----- -------- ----- 000 00000000 ram/ dia gnosis backup ram 003034 h tear1a[r] b,h,w 000 ----- -------- ----- 000 00000000 003038 h tear2a[r] b,h,w 000 ----- -------- ----- 000 00000000 00303c h taeara[r/w] b,h,w ----- 111 11111111 tasara[r/w] b,h,w ----- 000 00000000 d a t a s h e e t 110 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential address address offset value / register name block +0 +1 +2 +3 003040 h tfecra [r/w] b,h,w --- - 0000 ticra [r/w] b,h,w ---- 0000 ttcra [r/w] b,h,w ------ 00 00001100 ram/ diagnosis backup ram 003044 h tsrcra [r/w] b,h,w 0 ------- D D tkccra [r/w] b,h,w 00 ---- 00 003048 h to 0030fc h D reserved 003100 h busdigsr0[r/w] h,w 00000000 0 ----- 00 busdigsr1[ r/w] h,w 00000000 0 ----- 00 bus diagnosis 003104 h busdigsr2[r/w] h,w 00000000 0 ----- 00 buststr0[r/w] h,w 00 -- 0000 00000000 003108 h busadr0 [r] w 00000000 00000000 00000000 00000000 00310c h busadr1 [r] w 00000000 00000000 00000000 00000000 003110 h bus adr2 [r] w 00000000 00000000 00000000 00000000 003114 h D D busdigsr3[r/w] h,w 00000000 0 ----- 00 003118 h busdigsr4[r/w] h,w 00000000 0 ----- 00 buststr1[r/w] h,w 00 -- 000 - 00000000 00311c h D D D D 003120 h busadr3 [r] w 00000000 00000000 00000000 000000 00 003124 h busadr4 [r] w 00000000 00000000 00000000 00000000 003128 h to 003ffc h D reserved 004000 h to 005ffc h backup - ram backup ram area 006000 h to 00effc h D D D D reserved 00f000 h to 00fefc h D D D D reserved [s] 00ff00 h dsucr [r/w] b,h,w ----- --- ------- 0 D D ocdu [s] 00ff04 h to 00ff0c h D reserved [s] 00ff10 h pcsr [r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 111 confidential address address offset value / register name block +0 +1 +2 +3 00ff14 h pssr [r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00ff18 h to 00fff4 h D reserved [s] 00fff8 h edir1 [ r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00fffc h edir0 [r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx [s]: it is a system register. the illegal instruction exception (data access error) is generated in these registers in the user mode when r eading and writing to it. d a t a s h e e t 112 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? interrupt vector table this list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers. ? interrupt vector ? 64pin s interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexad ecimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instructi on access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd 4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15 ( f h ) fixed 3c0 h 000fffc0 h - error generati on during internal bus diagnosis xbs ram double - bit error generation backup ram double - bit error generation tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1 * 8 external low - voltage detection interrupt reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2 * 2 reload timer 3/6/7 19 13 icr03 3b0 h 000fffb0 h 3 * 2 multi - function serial interface ch . 0 (reception completed) 20 14 icr04 3ac h 000fffac h 4 * 1 multi - fun ction serial interface ch . 0 (status) multi - function serial interface ch . 0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5 * 1 - 22 16 icr06 3a4 h 000fffa4 h - * 7 - 23 17 icr07 3a0 h 000fffa0 h - * 7 - 24 18 icr08 39c h 000fff9c h - * 7 - 25 19 icr09 3 98 h 000fff98 h - * 7 multi - function serial interface ch . 3 (reception completed) 26 1a icr10 394 h 000fff94 h 10 * 1 multi - function serial interface ch . 3 (status) multi - function serial interface ch . 3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 multi - function serial interface ch . 4 (reception completed) 28 1c icr12 38c h 000fff8c h 12 * 1 multi - function serial interface ch . 4 (status) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 113 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexad ecimal multi - function serial interface ch . 4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 mul ti - function serial interface ch . 5 (reception completed) 30 1e icr14 384 h 000fff84 h 14 * 1 multi - function serial interface ch . 5 (status) multi - function serial interface ch . 5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15 multi - function ser ial interface ch . 6 (reception completed) 32 20 icr16 37c h 000fff7c h 16 * 1 multi - function serial interface ch . 6 (status) multi - function serial interface ch . 6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 370 h 000fff70 h - ram diagnosis end ram initialization completion error generation during ram diagnosis backup ram diagnosis end backup ram initialization completion error generation during backup ram diagnosis can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 real time clock 37 25 icr21 368 h 000fff68 h - - 38 26 icr22 364 h 000fff64 h - * 7 16 - bit free - run timer 0 (0 detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 ppg 1/10/11/20/30/31 40 28 icr24 35c h 000fff5c h 24 * 3 16 - bit free - run timer 1 (0 detection) / (compare clear) ppg 2/3/12/13/23/43 41 29 icr25 358 h 000fff58 h 25 * 3 16 - bit free - run timer 2 (0 detection) / (compare clear) p pg 4/24/35 42 2a icr26 354 h 000fff54 h 26 * 3 ppg 7/16/17/27/37 43 2b icr27 350 h 000fff50 h 27 * 3 ppg 19 44 2c icr28 34c h 000fff4c h 28 * 3 16 - bit icu 0 ( fetching ) / 16 - bit icu 1 ( fetching ) 45 2d icr29 348 h 000fff48 h 29 main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer 16 - bit icu 2 ( fetching ) /16 - bit icu 3 ( fetching ) clock calibration unit ( sub oscillation ) 47 2f icr31 340 h 000fff40 h 31 * 1, * 4 multi - function serial interface ch . 9 (reception completed) multi - function seria l interface ch . 9 (status) a/d converter 0/1/7/10/11/14/15/16/17/22/27/28/31 48 30 icr32 33c h 000fff3c h 32 d a t a s h e e t 114 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexad ecimal clock calibration unit ( cr oscillation ) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch . 9 (transmission complete d) 16 - bit ocu 0 ( match ) / 16 - bit ocu 1 ( match ) 32 - bit free - run timer 4 50 32 icr34 334 h 000fff34 h 34 * 6 16 - bit ocu 2 ( match ) / 16 - bit ocu 3 ( match ) 16 - bit ocu 4 ( match ) / 16 - bit ocu 5 ( match ) 51 33 icr35 330 h 000fff30 h 35 32 - bit icu6 ( fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36 * 1 multi - function serial interface ch . 10 (reception completed) multi - function serial interface ch . 10 (status) multi - function serial interface ch . 10 (transmission completed) 53 35 icr37 3 28 h 000fff28 h 37 32 - bit icu8 ( fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38 * 1 multi - function serial interface ch . 11 (reception completed) multi - function serial interface ch . 11 (status) 32 - bit icu9 ( fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1/ 2 wg dtti 0 32 - bit icu4 ( fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch . 11 (transmission completed) 32 - bit icu5 ( fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/34/35/37/38/40/41/42/43/44/45/46/47 32 - bit ocu7/11 ( match ) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu8/9 ( match ) 59 3b icr43 310 h 000fff10 h 43 - 60 3c icr44 30c h 000fff0c h - * 7 - 61 3d icr45 308 h 000fff08 h - - dmac0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos tm * 9 ) 64 40 - 2fc h 000ffefc h - system reserved (used for r ealos ) 65 41 - 2f8 h 000ffef8 h - used with the int instruction 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - note: it does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *1: it does not support a dma transfer by the status of the multi - function serial interface and i 2 c reception. *2: reload timer ch.4 to ch.7 do not support a dma transfer by the interrupt. *3: ppg ch.24 to ch.47 do not support a dma transfer by the interrupt. *4: the clock calibration unit does not support a dma transfer by the interrupt. *5: it does not support a dma transfer by the interrupt by the ram ecc bit error. *6: 32 - bit free - run timer ch.3, ch.4 and ch.5 do not support a dma transfer by the interrupt. *7: there is no resource corresponding to the interrupt level. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 115 confidential *8: it does not support a dma transfer by the external low - voltage detection interrupt. *9: realos is a trademark of spansion llc. d a t a s h e e t 116 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? 80 pins interrupt factor interrupt number in terrupt level offset default address for tbr rn decimal hexade cimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000f ffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instr uction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15 ( f h ) fixed 3c0 h 000fffc0 h - error generation during internal bus diagnosis xbs ram double - bit error generation backup ram double - bit error generation tpu violation external interrupt 0 - 7 16 10 icr00 3 bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1 * 8 external low - voltage detection interrupt reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2 * 2 reload timer 3/6/7 19 13 icr03 3b0 h 000fffb0 h 3 * 2 multi - function serial interface ch . 0 (reception completed) 20 14 icr04 3ac h 000fffac h 4 * 1 multi - function serial interface ch . 0 (status) multi - function serial interface ch . 0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5 * 1 - 22 16 icr06 3a4 h 000fffa4 h - * 7 - 23 17 icr0 7 3a0 h 000fffa0 h - * 7 multi - function serial interface ch . 2 (reception completed) 24 18 icr08 39c h 000fff9c h 8 * 1 multi - function serial interface ch . 2 (status) multi - function serial interface ch . 2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9 * 1 multi - function serial interface ch . 3 (reception completed) 26 1a icr10 394 h 000fff94 h 10 * 1 multi - function serial interface ch . 3 (status) multi - function serial interface ch . 3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 multi - fu nction serial interface ch . 4 (reception completed) 28 1c icr12 38c h 000fff8c h 12 * 1 multi - function serial interface ch . 4 (status) d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 117 confidential interrupt factor interrupt number in terrupt level offset default address for tbr rn decimal hexade cimal multi - function serial interface ch . 4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch . 5 (reception completed) 30 1e icr14 384 h 000fff84 h 14 * 1 multi - function serial interface ch . 5 (status) multi - function serial interface ch . 5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15 multi - function serial interfac e ch . 6 (reception completed) 32 20 icr16 37c h 000fff7c h 16 * 1 multi - function serial interface ch . 6 (status) multi - function serial interface ch . 6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 370 h 000fff70 h - ram diagnosis end ram initialization completion error generation during ram diagnosis backup ram diagnosis end backup ram initialization completion error generation during backup ram diagnosi s can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 real time clock 37 25 icr21 368 h 000fff68 h - - 38 26 icr22 364 h 000fff64 h - * 7 16 - bit free - run timer 0 (0 detection) / (compare clear) 39 27 icr23 360 h 000fff 60 h 23 ppg 1/10/11/20/30/31 40 28 icr24 35c h 000fff5c h 24 * 3 16 - bit free - run timer 1 (0 detection) / (compare clear) ppg 2/3/12/13/23/43 41 29 icr25 358 h 000fff58 h 25 * 3 16 - bit free - run timer 2 (0 detection) / (compare clear) ppg 4/5/15/24 /35 42 2a icr26 354 h 000fff54 h 26 * 3 ppg 7/16/17/26/27/37 43 2b icr27 350 h 000fff50 h 27 * 3 ppg 8/18/19/29 44 2c icr28 34c h 000fff4c h 28 * 3 16 - bit icu 0 ( fetching ) / 16 - bit icu 1 ( fetching ) 45 2d icr29 348 h 000fff48 h 29 main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer 16 - bit icu 2 ( fetching ) /16 - bit icu 3 ( fetching ) clock calibration unit ( sub oscillation ) 47 2f icr31 340 h 000fff40 h 31 * 1, * 4 multi - function serial interface ch . 9 (reception completed) multi - function serial interface ch . 9 (status) d a t a s h e e t 118 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential interrupt factor interrupt number in terrupt level offset default address for tbr rn decimal hexade cimal a/d converter 0/1/7/10/11/12/14/15/16/17/19/22/26/27/28/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit ( cr oscillation ) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch . 9 (transmis sion completed) 16 - bit ocu 0 ( match ) / 16 - bit ocu 1 ( match ) 32 - bit free - run timer 4 50 32 icr34 334 h 000fff34 h 34 * 6 16 - bit ocu 2 ( match ) / 16 - bit ocu 3 ( match ) 32 - bit free - run timer 5 51 33 icr35 330 h 000fff30 h 35 * 6 16 - bit ocu 4 ( mat ch ) / 16 - bit ocu 5 ( match ) 32 - bit icu6 ( fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36 * 1 multi - function serial interface ch . 10 (reception completed) multi - function serial interface ch . 10 (status) multi - function serial interface ch . 10 (transmission completed) 53 35 icr37 328 h 000fff28 h 37 32 - bit icu8 ( fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38 * 1 multi - function serial interface ch . 11 (reception completed) multi - function serial interface ch . 11 (status) 3 2 - bit icu9 ( fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1/ 2 wg dtti 0 32 - bit icu4 ( fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch . 11 (transmission completed) 32 - bit icu5 ( fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47 32 - bit ocu7/11 ( match ) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu8/9 ( match ) 59 3b icr43 310 h 000fff10 h 43 - 60 3c icr44 30c h 000fff0c h - * 7 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45 * 5 base timer 1 irq1 - - dmac 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos ) 64 40 - 2fc h 000ffefc h - system reserved (used for realos ) 65 41 - 2f8 h 000ffef8 h - used with the int instruction 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - note: it does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *1: it does not support a dma transfer by the status of the multi - function serial interface and i 2 c reception. *2: reload timer ch.4 to ch.7 do not support a dma transfer by the interrupt. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 119 confidential *3: ppg ch.24 to ch.47 do not support a dma transfer by the interrupt. *4: the clock calibration unit does not support a dma transfer by the interrupt. *5: it does not support a dma transfer by the interrupt by the ram ecc bit error. *6: 32 - bit free - run timer ch.3, ch.4 and ch.5 do not support a dma transfer by the interrupt. *7: there is no resource corresponding to the interrupt level. *8: it does not support a dma transfer by the external low - voltage detec tion interrupt. d a t a s h e e t 120 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? 100 pins interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system r eserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000ff fc8 h - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15 ( f h ) fixed 3c0 h 000fffc0 h - error generation during internal bus diagnosis xbs ram double - bit error generation backup ram double - bit error generation tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1 * 8 external low - voltage detection interrupt reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2 * 2 reload timer 2/3/6/ 7 19 13 icr03 3b0 h 000fffb0 h 3 * 2 multi - function serial interface ch. 0 (reception completed) 20 14 icr04 3ac h 000fffac h 4 * 1 multi - function serial interface ch. 0 (status) multi - function serial interface ch. 0 (transmission completed) 21 15 icr05 3 a8 h 000fffa8 h 5 * 1 multi - function serial interface ch. 1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6 * 1 multi - function serial interface ch. 1 (status) multi - function serial interface ch. 1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7 * 1 multi - function serial interface ch. 2 (reception completed) 24 18 icr08 39c h 000fff9c h 8 * 1 multi - function serial interface ch. 2 (status) multi - function serial interface ch. 2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9 * 1 multi - funct ion serial interface ch. 3 (reception completed) 26 1a icr10 394 h 000fff94 h 10 * 1 multi - function serial interface ch. 3 (status) multi - function serial interface ch. 3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 121 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal multi - function ser ial interface ch. 4 (reception completed) 28 1c icr12 38c h 000fff8c h 12 * 1 multi - function serial interface ch. 4 (status) multi - function serial interface ch. 4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch. 5 (reception completed) 30 1e icr14 384 h 000fff84 h 14 * 1 multi - function serial interface ch. 5 (status) multi - function serial interface ch. 5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15 multi - function serial interface ch. 6 (reception completed) 32 20 icr16 37c h 000fff7c h 16 * 1 multi - function serial interface ch. 6 (status) multi - function serial interface ch. 6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 370 h 000fff 70 h - ram diagnosis end ram initialization completion error generation during ram diagnosis backup ram diagnosis end backup ram initialization completion error generation during backup ram diagnosis can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch. 7 (reception completed) 38 26 icr22 364 h 000fff64 h 22 * 1 multi - function serial interface ch. 7 ( status) 16 - bit free - running timer 0 (0 detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function serial interface ch. 7 (transmission completed) ppg 1/10/11/20/21/30/31 40 28 icr24 35c h 000fff5c h 24 * 3 16 - bit free - run timer 1 (0 detection) / (compare clear) ppg 2/3/12/13/23/32/43 41 29 icr25 358 h 000fff58 h 25 * 3 16 - bit free - run timer 2 (0 detection) / (compare clear) ppg 4/5/14/15/24/25/35/44 42 2a icr26 354 h 000fff54 h 26 * 3 ppg 6/7/16/17/26/27/37 43 2b icr27 350 h 000fff50 h 27 * 3 ppg 8/9/18/19/28/29 44 2c icr28 34c h 000fff4c h 28 * 3 multi - function serial interface ch. 8 (reception completed) 45 2d icr29 348 h 000fff48 h 29 * 1 multi - function serial interface ch. 8 (status) 16 - bit icu 0 ( fetching ) / 16 - bit ic u 1 ( fetching ) d a t a s h e e t 122 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch. 8 (transmission completed) 16 - bit icu 2 ( fetching ) /16 - bit icu 3 ( fetching ) clock calibration unit ( sub oscillation ) 47 2f icr31 340 h 000fff40 h 31 * 1, * 4 multi - function serial interface ch. 9 (reception completed) multi - function serial interface ch. 9 (status) a/d converter 0/1/7/9/10/11/12/13/14/15/16 17/18/19/22/23/26/27/28/29/31 48 30 i cr32 33c h 000fff3c h 32 clock calibration unit ( cr oscillation ) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch. 9 (transmission completed) 16 - bit ocu 0 ( match ) / 16 - bit ocu 1 ( match ) 32 - bit free - run timer 4 50 32 icr34 334 h 000fff34 h 34 * 6 16 - bit ocu 2 ( match ) / 16 - bit ocu 3 ( match ) 32 - bit free - run timer 3/5 51 33 icr35 330 h 000fff30 h 35 * 6 16 - bit ocu 4 ( match ) / 16 - bit ocu 5 ( match ) 32 - bit icu6 ( fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36 * 1 multi - func tion serial interface ch. 10 (reception completed) multi - function serial interface ch. 10 (status) 32 - bit icu7 ( fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch. 10 (transmission completed) 32 - bit icu8 ( fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38 * 1 multi - function serial interface ch. 11 (reception completed) multi - function serial interface ch. 11 (status) 32 - bit icu9 ( fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg de ad timer underflow 0/1/2 wg dead timer reload 0/1/2 wg dtti 0 32 - bit icu4 ( fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch. 11 (transmission completed) 32 - bit icu5 ( fetching / measurement ) 5 7 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/ 47 32 - bit ocu 6/7/10/11 ( match ) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu 8/9 ( match ) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0 c h 44 base timer 0 irq1 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 123 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45 * 5 base timer 1 irq1 - - dmac 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved ( used for realos ) 64 40 - 2fc h 000ffefc h - system reserved ( used for realos ) 65 41 - 2f8 h 000ffef8 h - used with the int instruction 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - note: it does not support a dma transfer request c aused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *1: it does not support a dma transfer by the status of the multi - function serial interface and i 2 c reception. *2: reload timer ch.4 to ch.7 do not support a dma transfer by the interrupt. *3: ppg ch.24 to ch.47 do not support a dma transfer by the interrupt. *4: the clock calibration unit does not support a dma transfer by the interrupt. *5: it does not support a dma transfer by the interrupt by the ram ecc bi t error. *6: 32 - bit free - run timer ch.3, ch.4 and ch.5 do not support a dma transfer by the interrupt. *7: there is no resource corresponding to the interrupt level. *8: it does not support a dma transfer by the external low - voltage detection interrupt. d a t a s h e e t 124 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? 120pin s interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15 ( f h ) fixed 3c0 h 000fffc0 h - error generation during internal bus diagnosis xbs ram double - bit error generation backup ram double - bit error generation tpu violatio n external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1 * 8 external low - voltage detection interrupt reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2 * 2 reload timer 2/3/6/7 19 13 icr03 3b0 h 000fffb0 h 3 * 2 multi - function serial interface ch. 0 (reception completed) 20 14 icr04 3ac h 000fffac h 4 * 1 multi - function serial interface ch. 0 (status) multi - function serial interface ch. 0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5 * 1 multi - function serial interface ch. 1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6 * 1 multi - function serial interface ch. 1 (status) multi - function serial interface ch. 1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7 * 1 multi - function serial interface ch. 2 (reception completed) 24 18 icr08 39c h 000fff9c h 8 * 1 multi - function serial interface ch. 2 (status) multi - function serial interface ch. 2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9 * 1 multi - function serial interfa ce ch. 3 (reception completed) 26 1a icr10 394 h 000fff94 h 10 * 1 multi - function serial interface ch. 3 (status) multi - function serial interface ch. 3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 125 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal multi - function serial interface ch. 4 (reception completed) 28 1c icr12 38c h 000fff8c h 12 * 1 multi - function serial interface ch. 4 (status) multi - function serial interface ch. 4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch. 5 (reception co mpleted) 30 1e icr14 384 h 000fff84 h 14 * 1 multi - function serial interface ch. 5 (status) multi - function serial interface ch. 5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15 multi - function serial interface ch. 6 (reception completed) 32 20 icr16 37c h 000fff7c h 16 * 1 multi - function serial interface ch. 6 (status) multi - function serial interface ch. 6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 370 h 000fff70 h - ram diagnos is end ram initialization completion error generation during ram diagnosis backup ram diagnosis end backup ram initialization completion error generation during backup ram diagnosis can2 36 24 icr20 36c h 000f ff6c h - up/down counter 0 up/down counter 1 real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch. 7 (reception completed) 38 26 icr22 364 h 000fff64 h 22 * 1 multi - function serial interface ch. 7 (status) 16 - bit free - run timer 0 (0 detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function serial interface ch. 7 (transmission completed) ppg 0/1/10/11/20/21/30/31 40 28 icr24 35c h 000fff5c h 24 * 3 16 - bit free - run timer 1 (0 detection) / ( compare clear) ppg 2/3/12/13/22/23/32/33/42/43 41 29 icr25 358 h 000fff58 h 25 * 3 16 - bit free - run timer 2 (0 detection) / (compare clear) ppg 4/5/14/15/24/25/35/44 42 2a icr26 354 h 000fff54 h 26 * 3 ppg 6/7/16/17/26/27/37 43 2b icr27 350 h 000fff 50 h 27 * 3 ppg 8/9/18/19/28/29 44 2c icr28 34c h 000fff4c h 28 * 3 multi - function serial interface ch. 8 (reception completed) 45 2d icr29 348 h 000fff48 h 29 * 1 multi - function serial interface ch. 8 (status) 16 - bit icu 0 ( fetching ) / 16 - bit icu 1 ( fetchi ng ) d a t a s h e e t 126 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch. 8 (transmission completed) 16 - bit icu 2 ( fetching ) /16 - bit icu 3 ( fetching ) clock calibration unit ( sub oscilla tion ) 47 2f icr31 340 h 000fff40 h 31 * 1, * 4 multi - function serial interface ch. 9 (reception completed) multi - function serial interface ch. 9 (status) a/d converter 0/1/7/9/10/11/12/13/14/15/16 / 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit ( cr oscillation ) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch. 9 (transmission completed) 16 - bit ocu 0 ( match ) / 16 - bit ocu 1 ( match ) 32 - bit free - run timer 4 50 32 icr3 4 334 h 000fff34 h 34 * 6 16 - bit ocu 2 ( match ) / 16 - bit ocu 3 ( match ) 32 - bit free - run timer 3/5 51 33 icr35 330 h 000fff30 h 35 * 6 16 - bit ocu 4 ( match ) / 16 - bit ocu 5 ( match ) 32 - bit icu6 ( fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36 * 1 mult i - function serial interface ch. 10 (reception completed) multi - function serial interface ch. 10 (status) 32 - bit icu7 ( fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch. 10 (transmission completed) 32 - bit icu8 ( fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38 * 1 multi - function serial interface ch. 11 (reception completed) multi - function serial interface ch. 11 (status) 32 - bit icu9 ( fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0/1/2 wg dead timer reload 0/1/2 wg dtti 0 32 - bit icu4 ( fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch. 11 (transmission completed) 32 - bit icu5 ( fetching / measurem ent ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47 32 - bit ocu 6/7/10/11 ( match ) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu 8/9 ( match ) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 00 0fff0c h 44 base timer 0 irq1 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45 * 5 base timer 1 irq1 - - d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 127 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal dmac0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos ) 64 40 - 2fc h 000ffefc h - system reserved (used for realos ) 65 41 - 2f8 h 000ffef8 h - used with the int instruction 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - note: it does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *1: it does not support a dma transfer by the status of the multi - function serial interface and i 2 c reception. *2: reload timer ch.4 to ch.7 do not support a dma tr ansfer by the interrupt. *3: ppg ch.24 to ch.47 do not support a dma transfer by the interrupt. *4: the clock calibration unit does not support a dma transfer by the interrupt. *5: it does not support a dma transfer by the interrupt by the ram ecc bit erro r. *6: 32 - bit free - run timer ch.3, ch.4 and ch.5 do not support a dma transfer by the interrupt. *7: there is no resource corresponding to the interrupt level. *8: it does not support a dma transfer by the external low - voltage detection interrupt. d a t a s h e e t 128 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? 144pi n s interrupt factor interrupt number interru pt level offset default address for tbr rn decim al hexa decim al reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ff ff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error inter rupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of inv alid instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15 ( f h ) fixed 3c0 h 000fffc0 h - error generation during internal bus diagnosis xbs ram double - bit error generation backup ram double - bit error generation tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1 * 8 external low - voltage detection interrupt reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2 * 2 reload timer 2/3/6/7 19 13 icr03 3b0 h 000fff b0 h 3 * 2 multi - function serial interface ch. 0 (reception completed) 20 14 icr04 3ac h 000fffac h 4 * 1 multi - function serial interface ch. 0 (status) multi - function serial interface ch. 0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5 * 1 multi - function serial interface ch. 1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6 * 1 multi - function serial interface ch. 1 (status) multi - function serial interface ch. 1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7 * 1 multi - function serial interface ch. 2 (reception completed) 24 18 icr08 39c h 000fff9c h 8 * 1 multi - function serial interface ch. 2 (status) multi - function serial interface ch. 2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9 * 1 multi - function serial interface ch. 3 (reception completed) 26 1a icr10 394 h 000fff94 h 10 * 1 multi - function serial interface ch. 3 (status) multi - function serial interface ch. 3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 129 confidential interrupt factor interrupt number interru pt level offset default address for tbr rn decim al hexa decim al multi - function serial interface ch. 4 (rece ption completed) 28 1c icr12 38c h 000fff8c h 12 * 1 multi - function serial interface ch. 4 (status) multi - function serial interface ch. 4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch. 5 (reception completed ) 30 1e icr14 384 h 000fff84 h 14 * 1 multi - function serial interface ch. 5 (status) multi - function serial interface ch. 5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15 multi - function serial interface ch. 6 (reception completed) 32 20 icr16 3 7c h 000fff7c h 16 * 1 multi - function serial interface ch. 6 (status) multi - function serial interface ch. 6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 370 h 000fff70 h - ram diagnosis end ram initialization completion error generation during ram diagnosis backup ram diagnosis end backup ram initialization completion error generation during backup ram diagnosis can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch. 7 (reception completed) 38 26 icr22 364 h 000fff64 h 22 * 1 multi - function serial interface ch. 7 (status) 16 - bit fre e - run timer 0 (0 detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function serial interface ch. 7 (transmission completed) ppg 0/1/10/11/20/21/30/31/40/41 40 28 icr24 35c h 000fff5c h 24 * 3 16 - bit free - run timer 1 (0 detection) / (c ompare clear) ppg 2/3/12/13/22/23/32/33/42/43 41 29 icr25 358 h 000fff58 h 25 * 3 16 - bit free - run timer 2 (0 detection) / (compare clear) ppg 4/5/14/15/24/25/34/35/44 42 2a icr26 354 h 000fff54 h 26 * 3 ppg 6/7/16/17/26/27/36/37 43 2b icr27 350 h 0 00fff50 h 27 * 3 ppg 8/9/18/19/28/29/38/39 44 2c icr28 34c h 000fff4c h 28 * 3 d a t a s h e e t 130 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential interrupt factor interrupt number interru pt level offset default address for tbr rn decim al hexa decim al multi - function serial interface ch. 8 (reception completed) 45 2d icr29 348 h 000fff48 h 29 * 1 multi - function serial interface ch. 8 (status) 16 - bit icu 0 ( fetching ) / 16 - bit icu 1 ( fetching ) main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch. 8 (transmission completed) 16 - bit icu 2 ( fetching ) /16 - bit icu 3 ( fetching ) clock calibration uni t ( sub oscillation ) 47 2f icr31 340 h 000fff40 h 31 * 1, * 4 multi - function serial interface ch. 9 (reception completed) multi - function serial interface ch. 9 (status) a/d converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/19/20/21/22/23/2 4/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit ( cr oscillation ) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch. 9 (transmission completed) 16 - bit ocu 0 ( match ) / 16 - bit ocu 1 ( match ) 32 - bit fr ee - run timer 4 50 32 icr34 334 h 000fff34 h 34 * 6 16 - bit ocu 2 ( match ) / 16 - bit ocu 3 ( match ) 32 - bit free - run timer 3/5 51 33 icr35 330 h 000fff30 h 35 * 6 16 - bit ocu 4 ( match ) / 16 - bit ocu 5 ( match ) 32 - bit icu 6 ( fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36 * 1 multi - function serial interface ch. 10 (reception completed) multi - function serial interface ch. 10 (status) 32 - bit icu7 ( fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch. 10 (trans mission completed) 32 - bit icu8 ( fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38 * 1 multi - function serial interface ch. 11 (reception completed) multi - function serial interface ch. 11 (status) 32 - bit icu9 ( fetching / measurement ) 55 3 7 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1/ 2 wg dtti 0 32 - bit icu4 ( fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch. 11 (transmission completed) 32 - bit icu5 ( fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47 32 - bit ocu 6/7/10/11 ( match ) 58 3a icr42 314 h 000fff14 h 42 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 131 confidential interrupt factor interrupt number interru pt level offset default address for tbr rn decim al hexa decim al 32 - bit ocu8/9 ( match ) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0c h 44 base timer 0 irq1 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45 * 5 base timer 1 irq1 - - dmac 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved ( used for realos ) 64 40 - 2fc h 000ffefc h - system reserved ( used for realos ) 65 41 - 2f8 h 000ffef8 h - used with the int instruction 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - note: it does not suppo rt a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *1: it does not support a dma transfer by the status of the multi - function serial interface and i 2 c reception. *2: reload timer ch. 4 to ch.7 do not support a dma transfer by the interrupt. *3: ppg ch.24 to ch.47 do not support a dma transfer by the interrupt. *4: the clock calibration unit does not support a dma transfer by the interrupt. *5: it does not support a dma transfer by the interrupt by the ram ecc bit error. *6: 32 - bit free - run timer ch.3, ch.4 and ch.5 do not support a dma transfer by the interrupt. *7: there is no resource corresponding to the interrupt level. *8: it does not support a dma transfer by the external low - volt age detection interrupt. d a t a s h e e t 132 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? 176pin s interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 0 00fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15 ( f h ) fixed 3c0 h 000fffc0 h - error generation during internal bus diagnosis xbs ram double - bit error generation backup ram double - bit error ge neration tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1* 8 external low - voltage detection interrupt reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2 * 2 reload ti mer 2/3/6/7 19 13 icr03 3b0 h 000fffb0 h 3 * 2 multi - function serial interface ch. 0 (reception completed) 20 14 icr04 3ac h 000fffac h 4 * 1 multi - function serial interface ch. 0 (status) multi - function serial interface ch. 0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5 * 1 multi - function serial interface ch. 1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6 * 1 multi - function serial interface ch. 1 (status) multi - function serial interface ch. 1 (transmission completed) 23 17 icr07 3a0 h 0 00fffa0 h 7 * 1 multi - function serial interface ch. 2 (reception completed) 24 18 icr08 39c h 000fff9c h 8 * 1 multi - function serial interface ch. 2 (status) multi - function serial interface ch. 2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9 * 1 m ulti - function serial interface ch. 3 (reception completed) 26 1a icr10 394 h 000fff94 h 10 * 1 multi - function serial interface ch. 3 (status) multi - function serial interface ch. 3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 133 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal multi - fu nction serial interface ch. 4 (reception completed) 28 1c icr12 38c h 000fff8c h 12 * 1 multi - function serial interface ch. 4 (status) multi - function serial interface ch. 4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial i nterface ch. 5 (reception completed) 30 1e icr14 384 h 000fff84 h 14 * 1 multi - function serial interface ch. 5 (status) multi - function serial interface ch. 5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15 multi - function serial interface ch. 6 (reception completed) 32 20 icr16 37c h 000fff7c h 16 * 1 multi - function serial interface ch. 6 (status) multi - function serial interface ch. 6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17 can0 34 22 icr18 374 h 000fff74 h - can1 35 23 icr19 3 70 h 000fff70 h - ram diagnosis end ram initialization completion error generation during ram diagnosis backup ram diagnosis end backup ram initialization completion error generation during backup ram diagnosis can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch. 7 (reception completed) 38 26 icr22 364 h 000fff64 h 22 * 1 multi - function serial interfa ce ch. 7 (status) 16 - bit free - run timer 0 (0 detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function serial interface ch. 7 (transmission completed) ppg 0/1/10/11/20/21/30/31/40/41 40 28 icr24 35c h 000fff5c h 24 * 3 16 - bit f ree - run timer 1 (0 detection) / (compare clear) ppg 2/3/12/13/22/23/32/33/42/43 41 29 icr25 358 h 000fff58 h 25 * 3 16 - bit free - run timer 2 (0 detection) / (compare clear) ppg 4/5/14/15/24/25/34/35/44/45 42 2a icr26 354 h 000fff54 h 26 * 3 ppg 6/ 7/16/17/26/27/36/37/46/47 43 2b icr27 350 h 000fff50 h 27 * 3 ppg 8/9/18/19/28/29/38/39 44 2c icr28 34c h 000fff4c h 28 * 3 multi - function serial interface ch. 8 (reception completed) 45 2d icr29 348 h 000fff48 h 29 * 1 multi - function serial interface ch. 8 (status ) 16 - bit icu 0 ( fetching ) / 16 - bit icu 1 ( fetching ) d a t a s h e e t 134 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch. 8 (transmission completed) 16 - bit icu 2 ( fetching ) /16 - bit icu 3 ( fetching ) clock calibration unit ( sub oscillation ) 47 2f icr31 340 h 000fff40 h 31 * 1, * 4 multi - function serial interface ch. 9 (reception completed) multi - function serial interface ch. 9 (status) a/d converter 0/1/2/3/4/5/6/7/8/9/10/ 11/12/13/14/15/16 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit ( cr oscillation ) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch. 9 (transmission completed) 16 - bit ocu 0 ( match ) / 16 - bit ocu 1 ( match ) 32 - bit free - run timer 4 50 32 icr34 334 h 000fff34 h 34 * 6 16 - bit ocu 2 ( match ) / 16 - bit ocu 3 ( match ) 32 - bit free - run timer 3/5 51 33 icr35 330 h 000fff30 h 35 * 6 16 - bit ocu 4 ( match ) / 16 - bit ocu 5 ( match ) 32 - bit i cu6 ( fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36 * 1 multi - function serial interface ch. 10 (reception completed) multi - function serial interface ch. 10 (status) 32 - bit icu7 ( fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - f unction serial interface ch. 10 (transmission completed) 32 - bit icu8 ( fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38 * 1 multi - function serial interface ch. 11 (reception completed) multi - function serial interface ch. 11 (status) 3 2 - bit icu9 ( fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0/1/2 wg dead timer reload 0/1/2 wg dtti 0 32 - bit icu4 ( fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch. 1 1 (transmission completed) 32 - bit icu5 ( fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/ 47 32 - bit ocu 6/7/10/11 ( match ) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu 8/9 ( match ) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0c h 44 base timer 0 irq1 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 135 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn decimal hexadecimal base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45 * 5 base timer 1 irq1 - - dmac 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delay interrupt 63 3f icr47 300 h 000fff00 h - system reserved ( used for realos ) 64 40 - 2fc h 000ffefc h - system reserved ( used for realos ) 65 41 - 2f8 h 000ffef8 h - used with the int instruction 66 | 255 42 | ff - 2f4 h | 000 h 000ff ef4 h | 000ffc00 h - note: it does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *1: it does not support a dma transfer by the status of the multi - function serial interf ace and i 2 c reception. *2: reload timer ch.4 to ch.7 do not support a dma transfer by the interrupt. *3: ppg ch.24 to ch.47 do not support a dma transfer by the interrupt. *4: the clock calibration unit does not support a dma transfer by the interrupt. *5: it does not support a dma transfer by the interrupt by the ram ecc bit error. *6: 32 - bit free - run timer ch.3, ch.4 and ch.5 do not support a dma transfer by the interrupt. *7: there is no resource corresponding to the interrupt level. *8: it does not supp ort a dma transfer by the external low - voltage detection interrupt. d a t a s h e e t 136 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1 , * 2 v cc v ss - 0. 3 v ss +6. 0 v analog power supply voltage * 1 , * 2 av cc v ss - 0. 3 v ss +6. 0 v av rh av cc v cc analog reference voltage * 1 avrh v ss - 0. 3 v ss +6. 0 v avrh av cc input voltage * 1 v i v ss - 0. 3 v cc +0. 3 v analog pin input voltage * 1 v ia5 v ss - 0. 3 v cc +0. 3 v out put voltage * 1 v o v ss - 0. 3 v cc +0. 3 v maximum clamp current i clamp - 4.0 ma *6 total maximum clamp current |i clamp | - 2 0 ma *6 "l" level maximum output current * 3 i ol1 - 15 ma i ol2 - 30 ma "l" level average output current * 4 i olav1 - 4 ma i olav2 - 12 ma "l" level total output current * 5 i ol1 - 100 ma i ol2 - 120 ma "h" level maximum output current * 3 i oh1 - - 15 ma i oh2 - - 30 ma "h" level average output current * 4 i ohav1 - - 4 ma i ohav2 - - 12 ma "h" level total output current * 5 i oh1 - - 100 ma i oh2 - - 120 ma power consumption t a : - 40 c to +105 c p d - 882 mw *8 t a : - 40 c to +125 c - 675 mw *8 operating temperature t a - 40 +1 0 5 c - 40 +1 2 5 c *7 storage temperature tstg - 55 +150 c *1: these parameters are based on the condition that v ss =av ss =0.0v * 2 : caution must be taken that av cc , avrh do not exceed v cc upon power - on and under other ci rcumstances. * 3 : the m aximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. * 4 : the a verage output current is defined as the value of the average current flowing through any one of the corresp onding pins for a 10 ms period. the average value is the operation current the operation ratio. *5: the total output current is defined as the maximum current value flowing through all of corresponding pins. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 137 confidential * 6 : corresponding pins: all general - purpose ports except p035, 041, 093, 122 . use within recommended operating conditions. use at dc voltage (current). the + b signal should always be applied by connecting a limiting resistor between the + b signal and the microcontroller. the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + b signal is input. note that when the microcontroller drive current is lo w, such as in the low power consumption modes, the + b input potential can increase the potential at the v cc pin via a protective diode, possibly affecting other devices. note that if the + b signal is input when the microcontroller is off (not fixed at 0 v), since the power is supplied through the pin, the microcontroller may operate incompletely. note that if the +b signal is input at power - on, since the power is supplied through the pin, the power - on reset may not function in the power supply voltage . do not leave + b input pins open. *7: when it is used under this condition , contact your sales representative. *8: it is a standard when four - layer substrate is used. sample recommended circuit < warning > semiconductor d evices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. mb915 2 0 series + b input (12 to 16v) protective diode limiting resistor current d a t a s h e e t 138 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential 2. recommended operating conditions (v ss =av ss =0.0v) paramet er symbol value unit remarks min max power supply voltage v cc , av cc 4.5 5.5 v recommended operation guarantee range ( when 5.0v is used) 3 . 0 3 . 6 v recommended operation guarantee range ( when 3.3v is used) 2.7 5.5 v operation guarantee range *1 s moothing capacitor * 2 c s 4.7 ( tolerance within 50 % ) f use a ceramic capacitor or a capacitor that has the similar frequency characteristics. use a capacitor with a capacitance greater than c s as the smoothing capacitor on the vcc pin. operating temperat ure t a - 40 +1 0 5 c - 40 +1 2 5 c *3 *1: when it is used outside recommended operation guarantee range (range of the operation guarantee) ,contact your sales representative. moreover, minimum value with an effective external low - voltage detection reset be comes a voltage until generating low - voltage detection reset . * 2 : see the following diagram for details on the connection of smoothing capacitor c s . *3: when it is used under this condition , contact your sales representative. ? < warning > the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is mad e with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. c s c v ss av ss v ss d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 139 confidential 3. dc characteristics ( t a : - 40 c to +105 c , v cc = avcc =5.0v 10%/3.3v 0.3v, v ss =av ss =0.0v) para meter symb ol pin name conditions value unit remarks min typ max power supply current i cc 5 v cc operating frequency f cp =80mhz, fcpp=40mhz, at normal operation - 60 80 ma operatin g frequency f cp =80mhz, fcpp=40mhz, at flash write - 70 90 ma operating frequency f cp =80mhz, fcpp=40mhz, at flash erase - 70 90 ma operating frequency f cp =64mhz, fcpp=32mhz, at normal operation - 54 71 ma operating frequency f cp =64mhz, fcpp=3 2mhz, at flash write - 64 81 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash erase - 64 81 ma operating frequency f cp =48mhz, fcpp=24mhz, at normal operation - 46 62 ma operating frequency f cp =48mhz, fcpp=24mhz, at flash write - 56 72 ma operating frequency f cp =48mhz, fcpp=24mhz, at flash erase - 56 72 ma i ccs 5 operating frequency f cp =80mhz, fcpp=40mhz, at cpu sleep mode - 45 61 ma i ccbs 5 operating frequency f cp =80mhz, fcpp=40mhz, at bus sleep mode - 23 51 ma i cct 5 wa tch mode when using crystal 4mhz t a =+25 c * - 1500 2610 a when using built - in cr clock 50khz t a =+25 c * - 450 2000 when using sub clock 32khz t a =+25 c * - 460 2000 i cch 5 stop mode t a =+25 c * - 450 2000 a i cct 52 watch mode (p ower off ) when using crystal 4mhz t a =+25 c * - 1100 1300 a lvd/ rtc operation , backup ram 8kb retention when using built - in cr clock 50khz , t a =+25 c * - 77 267 when using sub clock 32khz t a =+25 c * - 100 285 i cch 52 stop mode (p ower off ) t a =+25 c * - 74 265 a backup ram 8kb retention d a t a s h e e t 140 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (t a : - 40 c to +125 c , v cc = avcc=5.0v 10%/3.3v ss =av ss =0.0v) para meter symb ol pin name conditions value unit remarks min typ max power supply current i cc 5 vcc operating frequency f cp =80mhz, fcpp=40mh z, at normal operation - 60 102 ma operating frequency f cp =80mhz, fcpp=40mhz, at flash write - 70 115 ma operating frequency f cp =80mhz, fcpp=40mhz, at flash erase - 70 115 ma operating frequency f cp =64mhz, fcpp=32mhz, at normal operation - 5 4 92 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash write - 64 105 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash erase - 64 105 ma operating frequency f cp =48mhz, fcpp=24mhz, at normal operation - 46 82 ma operating freq uency f cp =48mhz, fcpp=24mhz, at flash write - 56 95 ma operating frequency f cp =48mhz, fcpp=24mhz, at flash erase - 56 95 ma i ccs 5 operating frequency f cp =80mhz, fcpp=40mhz, at cpu sleep mode - 45 82 ma i ccbs 5 operating frequency f cp =80mhz, f cpp=40mhz, at bus sleep mode - 23 72 ma i cct 5 watch mode when using crystal 4mhz t a =+25 c * - 1500 2610 a when using built - in cr clock 50khz t a =+25 c * - 450 2000 when using sub clock 32khz t a =+25 c * - 460 2000 i cch 5 stop mode t a =+ 25 c * - 450 2000 a i cct 52 watch mode (p ower off ) when using crystal 4mhz t a =+25 c * - 1100 1300 a lvd/ rtc operation , backup ram 8kb retention when using built - in cr clock 50khz , t a =+25 c * - 77 267 when using sub clock 32khz t a =+25 c * - 100 285 i cch 52 stop mode (p ower off ) t a =+25 c * - 74 265 a backup ram 8kb retention d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 141 confidential (t a : - 4 0 c to +1 2 5 c , v cc = av cc = 5.0v 10% /vcc=av cc =3.3v 0.3v , v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max input lea k current i il all input pins v cc =av cc =5.5v v ss d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 143 confidential 4. ac characteristics (1) main clock timing (t a : - 4 0 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc =3 . 3 v 0.3v , v ss =av ss =0.0v ) parameter sym bol pin name con ditio ns value unit remarks min typ max source oscillation clock frequency f c x0, x1 - - 4 16 mhz source oscillation clock cycle time t cyl x0, x1 62.5 250 - ns internal operating clock frequency *1 f cp - 2 - 80 mhz cpu clock f c p p 1 40 peripheral bus clock f cp t 1 40 external bus clock (when v cc =5.0v is used) *2 1 32 external bus clock (when v cc =3.3v is used) internal operating clock cycle time *1 t cp - 12.5 - 500 ns cpu clock t c p p 25 1000 peripheral bus cloc k t cp t 25 1000 external bus clock (when v cc =5.0v is used) 31.25 1000 external bus clock (when v cc =3.3v is used) can pll jitter ( during lock ) t pj - - 10 - 10 ns f c p =80 mhz (4mhz ? ccr - 50 10 0 150 khz * 1 : the maximum / minimum value is defined when using the main clock and pll clock. *2: please use it with external load capacity 12pf or less for vcc=3.3v0.3v (40mhz operation). ? x0,x1 c lock timing x0 t cyl d a t a s h e e t 144 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? c an pll jitter deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 145 confidential (1 - 2) sub clock timing (t a : - 4 0 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =a v ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min typ max source oscillation clock frequency f c l x0 a , x1 a - - 32.768 - khz source oscillation clock cycle time t lc yl x0 a , x1 a - 30.52 - s ? x0a,x1a clock timing x0a t lcyl d a t a s h e e t 146 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? guaranteed operation range internal operation clock frequency vs. power supply voltage note: the power supply voltage, which is the low - voltage detection setting voltage or lower, is in the reset state. oscillation clock frequency vs. internal operation clock frequency internal operation clock frequency main clock pll clock multipli ed by 1 multipli ed by 2 multipli ed by 3 multipli ed by 4 ... multipli ed by 19 multi pli ed by 2 0 oscillation clock frequency 4mhz 2mhz 4mhz 8mhz 12mhz 16mhz ... 76 mhz 8 0 mhz ? example of oscillation circuit note: as to the product with its clock supervisor s initial value is on , when the oscillat or is unable to start within 20ms from the stop state the clock supervisor will detect the oscillatio n stop. as a result, the cpu moves to the fail safe operation . design your print circuit board so that the oscillat or can start oscillation within 20ms. moreover, it is recommended to be designed after the match evaluation of the circuit is requested to th e departure pendulum maker when the oscillation circuit is composed. internal operation clock frequency f cp (mhz) 80 4 2 2 .7 5.5 power supply voltage v cc (v) mb91f5 2 x guaranteed operation range pll guaranteed operation range 4.5 mb91f5 2 x recommended guaranteed operation range x1 x0 r=0 c2= 10 pf c1= 10 pf 4mhz d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 147 confidential ac characteristics are specified by the following measurement reference voltage values. ? input signal waveform ? output signal waveform hysteresis input pin (automotive) output pin h ysteresis input pin (cmos schmitt) 0.5vcc 0.8vcc 0.8v 2.4v 0.3vcc 0.7vcc d a t a s h e e t 148 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (2) reset input (t a : - 40 c to +1 2 5 c , v c c = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max reset input time t rstl rstx C C + 100 C C C between several hundred s and several ms, and for an external clock, the time is 0 ms. ? at stop mode 0.2 v cc 100 s rstx x0 90% of amplitude internal operation clock oscillation time of oscillator oscillation stabilization waiting time instruction execution internal reset 0.2 v cc t rstl rstx 0.2 v cc 0.2 v cc t rstl d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 149 confidential (3) power - on conditions (t a : - 40 c to +1 2 5 c , v ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max level detection voltage C cc C C cc C C C C C C C C C cc v cc = at level detection release level time C C off v cc C C C d a t a s h e e t 150 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ( 4 ) multi - function serial ( 4 - 1) csio timing (4 - 1 - 1) bit setting: smr: md2=0, smr: md1=1, smr : md0=0, smr: scinv=0 , scr:spi=0 (t a : - 40 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter symbol pin name cond itions value unit remarks min max serial clo ck cycle time t scyc sck0 to sck11 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck slov i sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot5 to sot11 - 30 30 ns sck3 , sck4 sot3 , sot4 - 300 300 ns valid sin setup time t ivsh i sck0 to sck2 , sck5 to sck11 sin0 to sin2 , sin5 to sin11 34 - ns sck3 , sck 4 sin3 , sin4 300 - ns sck shix i sck0 to sck 11 sin0 to sin11 0 - ns serial clock "h"pulse width t shsl sck0 to sck11 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse width t slsh 2t cp p - 10 - ns sck slov e sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot5 to sot11 - 33 ns sck3 , sck4 sot3 , sot4 - 300 ns valid sin setup time t ivsh e sck0 to sck11 sin0 to sin11 10 - ns sck shix e 20 - ns sck fall time t f sck0 to sck11 - 5 ns sck rise time t r sck0 to sck11 - 5 ns notes : ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal opera tion clock used and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 151 confidential ? internal shift clock mode ? external shift clock mode 2.4v 2.4v 0.8v 0.8v sinx sotx sckx t scyc t slovi t shixi t ivshi 0.8v v ih 1 v i l 1 v ih 1 v i l 1 2.4v v ih 1 0.8v sinx sotx sckx t slsh t slove t shixe t ivshe t shsl v il 1 t f t r v ih 1 v il 1 v ih 1 v il 1 v ih 1 v il 1 d a t a s h e e t 152 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (4 - 1 - 2 ) bit setting: smr: md2=0, smr: md1=1, smr : md0=0, smr: scinv= 1 , scr:spi=0 (t a : - 40 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter symbol pin name cond itions value unit remarks min max serial clock cycle time t scyc sck0 to sck11 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck s h ov i sck0 to sck2 , sck5 to s ck11 sot0 to sot2 , sot 5 to sot11 - 30 30 ns sck 3 , sck4 sot3 , sot4 - 300 300 ns valid sin setup time t ivs li sck0 to sck2 , sck5 to sck11 sin0 to sin2 , s in5 to sin11 34 - ns sck 3 , sck4 sin3, sin4 300 - ns sck s l ix i sck0 to sck 11 sin0 to sin11 0 - ns serial clock "h"pulse width t shsl sck0 to sck11 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse width t slsh 2t cp p - 10 - ns sck s h ov e sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot 5 to sot11 - 33 ns sck 3 , sck4 sot3 , sot4 - 300 ns valid sin setup time t ivs le sck0 to sck11 sin0 to sin11 10 - ns sck s l ix e 20 - ns sck fall time t f sck0 to sck11 - 5 ns sck rise time t r sck0 to sck11 - 5 ns notes: ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal operation clock used and other parameters. please use ch. 3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 153 confidential ? internal shift clock mode ? external shift clock mode 2.4v 0.8 v 2.4 v 0.8v sinx sotx sckx t scyc t s h ovi t s l ixi t ivs l i 2.4 v v ih 1 v i l 1 v ih 1 v i l 1 2.4v v ih 1 0.8v sinx sotx sckx t s h s l t s h ove t s l ixe t ivs l e t s l s h v il 1 t r t f v ih 1 v il 1 v ih 1 v il 1 v ih 1 v il 1 d a t a s h e e t 154 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (4 - 1 - 3) bit setting : smr : md2=0, smr:md1=1, smr : md0=0 , smr:scinv=0, scr:spi=1 (t a : - 40 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max serial clock cycle time t scyc sck0 to sck11 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck s h ov i sck 0 to sck2 , sck5 to sck 11 sot0 to sot2 , sot 5 to sot11 - 30 30 ns sck 3 , sck4 sot 3 , sot4 - 300 300 ns valid sin setup time t ivs li sck0 to sck2 , sck5 to sck11 sin0 to sin2 , s in5 to sin11 34 - ns sck 3 , sck4 sin3 , sin4 300 - ns sck s l ix i sck0 to sck 11 sin0 to sin11 0 - ns sot s ovli sck0 to sck11 sot0 to sot11 2t cp p - 30 - ns serial clock "h"pulse width t shsl sck0 to sck11 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse wid th t slsh 2t cp p - 10 - ns sck s h ov e sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot 5 to sot11 - 33 ns sck 3 , sck4 sot3 , sot4 - 300 ns valid sin setup time t ivsh e sck0 to sck11 sin0 to sin11 10 - ns sck s l ix e 20 - ns sck fall time t f sck0 to sck11 - 5 ns sck rise time t r sck0 to sck11 - 5 ns notes: ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal operation clock used and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 155 confidential ? internal shift clock mode ? external shift clock mode *: it writes in the tdr register and, then, it changes. t ivshe t scyc t shovi t sovli t slixi t ivsli 2.4v 2.4v 0.8v 0.8v v ih v il v ih v il 2.4v 0.8v 0.8v sckx sotx sinx t slsh t shsl t shove t r t f t slixe t ivsle 2.4v 0.8v v ih v il v il v il v il v ih v ih v ih v ih v il 2.4v 0.8v sckx * sotx sinx d a t a s h e e t 156 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (4 - 1 - 4) bit setting : smr : md2=0, smr:md1=1, smr : md0=0 , smr:scinv=1, scr:spi=1 (t a : - 40 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av c c = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max serial clock cycle time t scyc sck0 to sck11 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck s l ov i sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot 5 to sot11 - 30 30 ns sck 3 , sck4 sot 3 , sot4 - 300 300 ns valid sin ivs hi sck 0 to sck2 , sck5 to sck11 sin0 to sin2 , s in5 to sin11 34 - ns sck 3 , sck4 sin3 , sin4 300 - ns sck s h ix i sck0 to sck 11 sin0 to sin11 0 - ns sot s ovhi sck0 to sck11 sot0 to sot11 2t cp p - 30 - ns serial clock "h"pulse width t shsl sck0 to sck11 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse widt h t slsh 2t cp p - 10 - ns sck s l ov e sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot 5 to sot11 - 33 ns sck 3 , sck4 sot3 , sot4 - 300 ns valid sin ivsh e sck0 to sck11 sin0 to sin11 10 - ns sck shix e 20 - ns sck fall time t f sck0 to sck11 - 5 ns sck rise time t r sck0 to sck11 - 5 ns notes: ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by int ernal operation clock used and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 157 confidential ? internal shift clock mode ? external shift clock mode *: it writes in the tdr register and, then, it changes. t f t scyc t slovi t sovhi t shixi t ivshi 2.4v 2.4v 2.4v 0.8v 0.8v v ih v il v ih v il 2.4v 0.8v sckx sotx sinx t slsh t shsl t slove t r t f t shixe t ivshe 2.4v 0.8v v ih v il v il v il v il v ih v ih v ih v ih v il 2.4v 0.8v sckx * sotx sinx d a t a s h e e t 158 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (4 - 1 - 5) bit setting : smr:md2=0, smr:md1=1, smr:md0=0 , when serial chip select is used : s cscr:csen=1, serial clock output mark level "h" : smr,scsfr:scinv=0, serial chip select inactive level "h" : scscr,scsfr:cslvl=1 (t a : - 4 0 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con diti o ns value unit remarks min max scs cssi sck 1, sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - t cssu - 50 * 1 t cssu +0 * 1 ns internal shift clock mode output pin : c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 t cssu - 50 * 1 t cssu + 30 0 * 1 ns sck cs hi sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t cshd - 1 0 * 2 t cshd + 50 * 2 ns sck3 , sck4 scs3 , scs40 to scs43 t cshd - 300 * 2 t cshd +50 * 2 ns scs d eselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t csds - 50 *3 t csds +50 *3 ns scs css e sck 1 to sck11 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs 70 to scs73, s cs8 to scs11 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 3t cpp +30 - ns scs dse scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, scs8 to scs11 sot1 , sot2 , sot5 to sot11 - 40 ns scs3, scs40 to scs43 sot3 , sot4 - 300 ns d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 159 confidential parameter sym bol pin name con ditio ns value unit rem arks min max scs sot delay time t dee scs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, scs8 to scs11 sot1 to sot11 - +0 - ns external shift clock mode output pin: c l = 5 0pf sck scs clock switch time t scc sck 1 , sc k2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pin: c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 3t cpp - 300 3t cpp +50 ns *1: t cssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select timing operating clock regardless of the deselect time setting, once after the serial chi p select pin becomes inactive, it will take at least five p eripheral bus clock cycles to be active again please see the hardware manual for details of above - mentioned *1,*2, and *3. d a t a s h e e t 160 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential when serial chip select is used , seri al clock output mark level " h " , serial chip select inactive level "h" external shift clock mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "h" internal shift clock mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "h" internal shift clock mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 161 confidential (4 - 1 - 6) bit setting : smr:md2=0, smr:md1 =1, smr:md0=0 , when serial chip select is used : scscr:csen=1, serial clock output mark level "l" : smr,scsfr:scinv=1, serial chip select inactive level "h" : scscr,scsfr:cslvl=1 (t a : - 40 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max scs cssi sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - t cssu - 50 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 t cssu - 50 *1 t cssu + 30 0 *1 ns sck cs hi sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t cshd - 1 0 * 2 t cshd + 50 * 2 ns sck3 , sck4 scs3 , scs40 to scs43 t cshd - 300 * 2 t cshd +50 * 2 ns scs deselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t csds - 50 *3 t csds +50 *3 ns scs css e sck 1 to sck11 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, s cs70 to scs73, s cs8 to scs11 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 3t cpp +30 - ns scs dse scs1 , scs2 , scs50 to scs53 , scs60 to scs63 , scs70 to scs73 , scs8 to scs11 sot1 , sot2 , sot5 to sot11 - 40 ns scs3 , scs40 to scs43 sot3 , sot4 - 300 ns d a t a s h e e t 162 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential parameter sym bol pin name con ditio ns value unit r emarks min max scs sot delay time t dee s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 sot1 to sot11 - +0 - ns external shift clock mode output pin: c l = 5 0pf sck scs clock switch time t scc sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pin: c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 3t cpp - 300 3t cpp +50 ns *1: t c ssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select timing operating clock regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least five p eripheral bus clock cycles to be active again please see the hardware manual for details of above - mentioned *1,*2, and *3 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 163 confidential when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level "h" internal shift clock mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi when serial chip select is used , serial clock output mark level " l " , serial chip select inactive le vel "h" external shift clock mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level "h" internal shift clock mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc d a t a s h e e t 164 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (4 - 1 - 7) bit setting : smr:md2=0, smr :md1=1, smr:md0=0 , when serial chip select is used : scscr:csen=1, serial clock output mark level "h" : smr,scsfr:scinv=0, serial chip select inactive level "l" : scscr,scsfr:cslvl=0 (t a : - 4 0 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max scs cssi sck 1 , sck2, sck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - t cssu - 5 0 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 t cssu - 5 0 *1 t cssu + 30 0 *1 ns sck cs hi sck 1 to sck2, sck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t cshd - 1 0 *2 t cshd + 5 0 *2 ns sck3 , sck4 scs3 , scs40 to scs43 t cshd - 300 *2 t cshd + 5 0 *2 ns sc s deselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t csds - 50 *3 t csds +50 *3 ns scs css e sck 1 to sck11 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 3t cpp +30 - ns scs dse s cs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 sot1 , sot2 , sot5 to sot11 - 40 ns scs3 , scs40 to scs43 sot3 , sot4 - 300 ns d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 165 confidential parameter sym bol pin name con ditio ns value unit remarks min max scs sot delay time t dee scs1 to ~scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, scs8 to scs11 sot1 to sot11 - +0 - ns external shift clock mode output pin: c l = 5 0pf sck scs clock switch time t scc sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pin: c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 3t cpp - 30 0 3t cpp +50 ns *1: t cssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select timing operating clock regardless of the deselect time setting, once after the seria l chip select pin becomes inactive, it will take at least five p eripheral bus clock cycles to be active again please see the hardware manual for details of above - mentioned *1,*2, and *3. d a t a s h e e t 166 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level " l " internal s hift clock mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level " l " external shift clock mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t csh e t csde t dse t dee when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "l " internal shift clock mode , example of switching clock by round operation (x,y= 0,1,2,3) scsy output s ck output scsx output t scc d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 167 confidential (4 - 1 - 8) bit setting : smr:md2=0, sm r:md1=1, smr:md0=0 , when serial chip select is used : scscr:csen=1, serial clock output mark level "l" : smr,scsfr:scinv=1, serial chip select inactive level "l" : scscr,scsfr:cslvl=0 (t a : - 4 0 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max scs cssi sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - t cssu - 5 0 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 t cssu - 5 0 *1 t cssu + 30 0 *1 ns sck cs hi sck 1 , sck2, s ck5 to sck11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t cshd - 1 0 *2 t cshd + 5 0 *2 ns sck3 , sck4 scs3 , scs40 to scs43 t cshd - 300 *2 t cshd + 5 0 *2 ns scs deselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 t csds - 50 *3 t csds +50 *3 ns scs css e sck 1 to sck11 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, s cs70 to scs73, s cs8 to scs11 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 3t cpp +30 - ns scs dse s cs1 , scs2, scs50 ~ scs53, scs60 ~ scs63, scs70 ~ scs73, s cs8 ~ scs11 sot1 , sot2 , sot5 ~ sot11 - 40 ns scs3 , scs40~scs 43 sot3 ,sot4 - 300 ns d a t a s h e e t 168 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential parameter sym bol pin name con ditio ns value unit remarks min ma x scs sot delay time t dee scs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, scs8 to scs11 sot1 to sot11 - +0 - ns external shift clock mode output pin: c l = 5 0pf sck scs clock switch time t scc sck 1 , sck2, s ck5 to sck 11 scs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pin: c l = 5 0pf sck3 , sck4 scs3 , scs40 to scs43 3t cpp - 300 3t cpp +50 *1: t cssu =scstr:cssu7 - 0 se rial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select timing operating clock regardless of the deselect time setting, once after the serial chip select pin beco mes inactive, it will take at least five p eripheral bus clock cycles to be active again please see the hardware manual for details of above - mentioned *1,*2, and *3. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 169 confidential when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level "l " master mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level " l " slave mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip se lect is used , serial clock output mark level " l " , serial chip select inactive level "l " master mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc d a t a s h e e t 170 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (4 - 2) uart ( asynchronous serial interface ) t iming bit se tting : smr : md2=0, smr:md1= 0 , smr : md0=0 bit setting : smr : md2=0, smr:md1= 0 , smr : md0= 1 when external clock is selected (bgr:ext=1) (t a : - 4 0 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter symb ol pin name conditio ns va lue unit remarks min max serial clock "l" pulse width t slsh sc k0 to sck11 - t cp p +10 - ns output pin: c l = 5 0pf serial clock "h"pulse width t shsl t cp p +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns (4 - 3) lin interfa ce (v2.1)( asynchronous serial interface for lin (v2.1)) timing bit setting : smr : md2=0, smr:md1= 1 , smr : md0= 1 (t a : - 40 c to +1 2 5 c , v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter symb ol pin name conditio ns value unit remarks min m ax serial clock "l" pulse width t slsh sc k0 to sck11 - t cp p +10 - ns output pin: c l = 5 0pf serial clock "h"pulse width t shsl t cp p +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns when external clock is selected sck t s hsl v il v ih v ih t r t slsh t f v il v ih v il when external clock is selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 171 confidential ( 4 - 4 ) i 2 c t iming (t a : - 4 0 c to +1 2 5 c , v c c = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v ) parameter sym bol pin name conditions standard mode high - speed mode * 3 unit rem arks min max min max scl clock frequency f scl sck 3 to sck11 c l =50pf r = (v p /i ol ) *1 0 100 0 400 khz repeat "start" condition hold time sda scl hdsta sot 3 to sot11, (sda) sck 3 to sck11, (scl) 4 .0 C C low sck 3 to sck11, (scl) 4.7 C C high sck 3 to sck11, (scl) 4 .0 C C susta sck 3 to sck11, (scl) 4.7 C C hddat sot 3 to sot11, (sda) sck 3 to sck11, (scl) 0 3.45 *2 0 0.9 *3 sudat sot 3 to sot11, (sda) sck 3 to sck11, (scl) 250 C C susto sot 3 to sot11, (sda) sck 3 to sck11, (scl) 4 .0 C C buf C C C s p C C cpp * 4 C cpp * 4 C l represent the pull - up resistance and load capacitance of the scl and sda output lines, respect ively. vp shows that the power - supply voltage of the pull - up resistor and i ol shows the v ol guarantee current. *2: the maximum t hddat only has to be met if the device does not extend the " l " width (t low ) of the scl signal . *3: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4: t cpp is the peripheral clock cycle time. adjust the clock of the bus in the surrounding to 8mhz or more when use i 2 c. d a t a s h e e t 172 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? i 2 c tim ing sda scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 173 confidential ( 5 ) timer input timing (t a : - 4 0 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tin0 to tin7 ic u0 to icu9 frck0 to frck5 tioa 0 , tio a1, tio b0 , tio b1, ain0 , ain1, bin0 , bin1, zin0 , zin1 C cp p C ? timer input timing ( 6 ) trigger input timing (t a : - 4 0 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl int0 to int15 , adtg , rx0 , rx1 , rx2 C cp p C C ? trigger input timing v ih v il t tiwl t tiwh v il tinx , icux , frck x , tioax,tiobx ain x ,bin x , zin x v ih v ih v il adtg t trgl t trgh v il intx rxx v ih d a t a s h e e t 174 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ( 7 ) nmi input timing (t a : - 40 c to +1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v ) parameter symbol pin name conditions value unit remarks min max input pulse width t nmil nmix C c p p C ? nmix input timing v ih 5 nmix t nmil v ih 5 v il 5 v il 5 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 175 confidential (8) low voltage detection (external low - voltage detection) (t a : - 40 c to +1 2 5 c , v ss =av ss =0.0v) parameter symbol pin name conditi ons value unit remarks min typ max power supply voltage range v dp5 vcc - 2. 7 - 5.5 v detection voltage v d l * 1 - 8% 2.8 +8% v when power - supply voltage falls and detection level is set initially hysteresis width v hys - - 0.1 - v when power - supply voltage rises low voltage detection time td - - - 30 s power supply voltage regulation - vcc - - 2 - 2 v/ms *2 * 1 : if the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to genera te or release after the power supply voltage has exceeded the detection voltage range. *2: please suppress the change of the power supply within the range of the power - supply voltage regulation to do a low voltage detection by detecting voltage ( v d l ). (9 ) low voltage detection (internal low - voltage detection) (t a : - 4 0 c to +1 2 5 c , v ss =av ss =0.0v) parameter symbol pin name con ditio ns value unit remarks min typ max power supply voltage range v rd p5 - - 0.6 - 1.4 v detection voltage v rd l * 0.8 0.9 1 .0 v when power - supply voltage fall s hysteresis width v rh ys - - 0.1 - v when power - supply voltage rises low voltage detection time - - - - 3 0 s *: if the fluctuation of the power supply is faster than the low voltage detection time, there is a possi bility to generate or release after the power supply voltage has exceeded the detection voltage range. d a t a s h e e t 176 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (10) external bus i/f (synchronous mode) timing (t a : - 40 c to +105 c , v cc =av cc =5.0v10% / v cc = av cc = 3.3 v 0.3v , v ss =av ss =0.0v) ( external load capacitance 50pf) parameter symbol pin name value unit remarks min max cycle time t cyc sysclk 25 - ns v cc = 5.0v *1 31.25 v cc = 3.3v chasl , t chash sysclk asx 0.5 18 ns cs0x to cs3x delay time t chcsl , t chcsh sysclk cs0x to cs3x 0.5 18 ns a00 to a21 delay time t chav , t chax sysclk a00 to a21 0.5 18 ns rdx delay time t chrl , t chrh sysclk rdx 0.5 18 ns rdx minimum pulse t rlrh rdx t cyc 2 - 20 - ns rwt=1, set rwt to 1 or more. * 2 data setup rdx dsrh rdx d16 to d31 18+ t cyc - ns same as above rdx rhdh 0 - ns wrnx delay time t chwl , t chwh sysclk wr0x, wr1x 0.5 18 ns wrnx minimum pulse t wlwh wr0x, wr1x t cyc - 10 - ns wwt=0 *2 sysclk chdv sysclk d16 to d31 0.5 18 ns sysclk chdx - 18 ns set wrcs to 1 or more. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 177 confidential parameter symbol pin name value unit remarks min max sysclk address output time t chmav sysclk d16 to d31 0.5 18 ns sysclk address hold time t chmax - 18 ns in multiplex mode, set as follows: ? set cswr and csrd to 2 or more. ? ascy must sat isfy the following conditions because of setting adcy > ascy and protocol violation prevention. adcy +1 acs + csrd adcy +1 acs + cswr ascy + 1 acs + csrd ascy + 1 acs + cswr see hardware manual for details. * 1 : please use it with external load ca pacity 12pf or less for vcc=3.3v0.3v (40mhz operation). * 2 : if the bus is expanded by automatic wait insertion or rdy input, add time (t cyc the number of expanded cycles) to the rated value. d a t a s h e e t 178 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential external bus i/f (synchronous mode, read operation, and mul tiplex mode) timing external bus i/f (synchronous mode, read operation, and split mode) timing cs0x to cs3x cs0x to cs 3x cs0x to cs3x d16 to d31 d16 to d31 a00 to a21 valid address read data t1 t2 t3 sysclk asx cs0x~cs3x rdx d16~d31 tchasl tchash tchcsl tchcsh tchrl tchrh tchmax trhdh t cyc tdsrh trlrh t4 csrd=2 adcy=1 rwt=1 tchmav ascy=0 acs=0 rdcs=0 valid address read data t1 t2 t3 sysclk asx cs0x~cs3x rdx a00~a21 d16~d31 tchcsh tchrl tchrh tchav tchax trhdh tdsrh trlrh t4 csrd=0 rwt=1 tchcsl t cyc acs=0 rdcs=0 tchasl tchash ascy=0 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 179 confidential ext ernal bus i/f (synchronous mode, write operation, and multiplex mode) timing external bus i/f (synchronous mode, write operation, and split mode) timing cs0x to cs3x wr0x to wr1x d16 to d31 cs0x to cs3x wr0x to wr1x d16 to d31 a00 to a21 valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x d16~d31 tchasl tchash t cyc tchcsl tchcsh tchwl tchwh tchdv tchdx twlwh adcy=1 cswr=2 t4 wrcs=1 tchmav wwt=0 acs=0 ascy=0 valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x a00~a21 d16~d31 tchcsh tchwl tchwh tchav tchax tchdx twlwh cswr=0 t4 wrcs=1 tchdv tchasl t cyc tchash ascy=0 tchcsl acs=0 wwt=0 d a t a s h e e t 180 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (11) external bus i/f ( a synchronous mode) timing (t a : - 40 c to +105 c , v cc =av cc =5.0v10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) ( external load capacitance 50pf) parameter symbol pin name value unit remar ks min max cycle time t cyc sysclk 25 - ns v cc = 5.0v *1 31.25 v cc = 3.3v rdx asrh rdx a00 to a21 2 t cyc - 12 2 t cyc + 12 ns rwt=1 , set rwt to 1 or more. *2 rdx rhah t cyc - 12 t cyc + 12 ns set rdcs t o 1 or more . data setup rdx dsrh rdx d16 to d31 18 + t cyc - ns rwt=1, set rwt to 1 or more. rdx rhdh 0 - ns address setup wrnx aswh wr0x to wr1x a00 to a21 t cyc - 12 t cyc + 12 ns wwt=0 *2 wrnx whah t cyc - 1 2 t cyc + 12 ns set wrcs to 1 or more. data setup wrnx dswh wr0x to wr1x d16 to d31 t cyc - 16 t cyc + 16 ns wwt=0 *2 wrnx whdh t cyc - 16 t cyc + 16 ns set wrcs to 1 or more. address setup asxtime masash asx d16 to d31 t cyc - 16 t cyc + 16 ns ascy=0 asx mashah t cyc - 16 t cyc + 16 ns in multiplex mode, set as follows: ? ? cyc the number of expanded cycles) to the rated value. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 181 confidential external bus i/f (asynchronous mode, read operation, and multiplex mode) timing external bus i/f (asynchronous mode, read operation, and split mode) timing cs0x to cs3x d16 to d31 a00 to a21 cs0x to cs3x d16 to d31 valid address t1 t2 t3 sysclk asx cs0x~cs3x rdx d16~d31 csrd=2 adcy=1 t4 read data rwt=1 trhdh tdsrh t5 rdcs=1 tmasash tmashah acs=0 ascy=0 t cyc t1 t2 t3 sysclk asx cs0x~cs3x rdx a00~a21 d16~d31 csrd=0 t4 read data valid address rwt=1 trhdh tdsrh t5 rdcs=1 tasrh trhah acs=0 ascy=0 t cyc d a t a s h e e t 182 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential external bus i/f (asynchronous mode, write operation, and multiplex mode) timing external bus i/f (asynchronous mode, write operation, and split mode) timing cs0x to cs3x d16 to d31 cs0x to cs3x d16 to d31 a00 to a21 wr0x to wr1x cs0x to cs3x wr0x to wr1x valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x d16~d31 wrcs=1 adcy=1 t4 cswr=2 tmasash tmashah tdswh twhdh ascy=0 acs=0 wwt=0 t cyc valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x a00~a21 d16~d31 wrcs=1 t4 cswr=0 taswh twhah tdswh twhdh ascy=0 acs=0 wwt=0 t cyc d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 183 confidential (12) external bus i/f (ready) timing (t a : - 40 c to +105 c , v cc =av cc =5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) ( ext ernal load capacitance 50pf) parameter symbol pin name value unit remarks min max cycle time t cyc sysclk 50 - ns if using rdy, set sysclk to 20 mhz or less. rdy setup time sysclk rdys sysclk , rdy 28 - ns sysclk rdyh sysclk , rdy 0 - ns external bus i/f (ready) timing auto wait cycle added cycle by rdy t3 t4 t5 sysclk asx cs0x~cs3x rdx rdy trdys trdyh t6 rwt=2 csrd=2 ascy=0 acs=0 rdcs=0 t1 t2 t cyc d a t a s h e e t 184 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential 5. a/d converter (1) 12 - bit a/d converter electrical characteristics (t a : - 4 0 c to +1 2 5 c , v cc =av cc =5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v ) parameter sym bol pin name value unit remarks min t yp max resolution - - - - 12 bit total error - - - - 12 lsb l inearity error - - - - 4.0 lsb differential linearity error - - - - 1.9 lsb zero transition voltage v ot an0 to an 47 av rl - 11.5 lsb - av rl + 12.5 lsb v 1lsb= (v fst - v ot )/ 4094 full - scale transition voltage v fst an0 to an 47 av rh - 13 . 5 lsb - av rh+ 10 . 5 lsb v sampling time t smp - 0.7 - - s *1 compare time t cmp - 0.7 - - s * 1 a/d conversion time t cnv - 1.4 - - s * 1 analog port input current i ain an0 to an47 - 1.0 - +1.0 a v avss ain avcc analog input voltage v ain an0 to an 47 av rl - av rh v reference voltage avr h av rh 3.0 - 5.5 v avr l avss/ avrl - 0.0 - v power supply current i a avcc * 3 - 0.47 0.63 m a per unit t a : +105 c - 0.47 0.7 m a per unit t a : +125 c i ah - - 2.5 a *2 i r avrh - 1 1.96 m a per unit i rh - - 1.6 a *2 variation between channels - an0 to an 47 - - 4 lsb *1 : time for each channel. *2: power supply current (v cc = av cc = 5.0 v) is specified if a/d converter is not operating and cpu is stopp ed. *3: the power supply current described only current value on a/d converter. the total avcc current value must be calculated the power supply current for a/d converter and d/a converter. ( n ote) please use the clock of 0.5 mhz - 20 mhz for the output clock of a/d converter to guarantee accuracy. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 185 confidential (2) definition of a/d converter terms resolution : analog variation that is recognized by an a/d converter. linearity error : deviation of the actual conversion characteristics from a straight line that connec ts the zero transition point (" 00 00 0000 000 0" " 1111 1110" " linearity error of digital output n = v nt - {1lsb (n - 1) + v ot } [lsb] 1lsb differential linearity error of digital output n = v (n + 1) t - v nt - 1 lsb [lsb] 1 lsb 1lsb = v fst - v ot [v] 4094 v ot : voltage at which the digital output changes from 000 h to 001 h . v fst : voltage at which the digital output changes from f fe h to f ff h . d a t a s h e e t 186 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential (3) notes on using a/d converter d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 187 confidential 6. f lash memory (1) electrical characteristics parameter value unit remarks min typ max sector erase time C 200 800 ms 8 kbyte s sector * 1 , excluding internal preprogramming time C 300 1100 m s 8 kbyte s sector * 1 , in cluding internal preprogramming time C 400 2000 m s 64 kbyte s sector * 1 , excluding internal preprogramming time C 700 3700 m s 64 kbyte s sector * 1 , in cluding internal preprogramming time 8 - bit writing time C 9 288 s exclusive of overhead time at system level * 1 16 - bit writing time C 12 384 s exclusive of overhead time at system level * 1 ecc writing time C 9 288 s exclusive of overhead time at system level * 1 erase cycle * 2 / data retain time 1 , 000 cycles/ 20 years , 10 , 000 cycles/ 10 years , 100 , 000 cycles/ 5 years C C C average t a =+85 c* 3 *1: the guaranteed value for erasure up to 100,000 cycle s . *2: number of erase cycles for each sector. *3: this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 8 5c). (2) notes while the flash memory is written or erased , shutdown of the external power (vcc) is prohibited. in the application system where vcc might be shut down while writing or erasing , be sure to turn the power off by using an external voltage detection function . to put it concretely, after the external power supply voltage falls below the detection voltage (v dl * ), hold vcc at 2.7v or more within the duration calculated by the following expression: td * [ s ] + (period of pclk [ s ] 257) + 50 [ s ] *: see 4.ac characteristics ( 8 ) low - voltage detection (external low - voltage detection) d a t a s h e e t 188 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential 7. d/a converter (t a : - 40 c to +1 2 5 c , v c c =av cc =5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter symbol pin name condition value unit remarks min ty p max resolution - - C C C 8 bit differential linearity error - - C C C 3.0 lsb conversion time - - C 0.47 0.58 0.69 s c l =20 C 2.37 2.90 3.43 s c l =100 output impedance ro da0, da1 C 3.1 3.8 4.5 k power supply current * 1 ia avcc C C 475 5 80 a e ach channel iah avcc C C C 7.5 a when powerdown e ach channel *1: the power supply current described only current value on d/a converter. the total avcc current value must be calculated the power supply current for d/a converter and a/d converte r. d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 189 confidential ? example characteristics this characteristic is an actual value of the arbitrary sample. it is not the guaranteed value. ? mb91f526 d a t a s h e e t 190 mb91f526 l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential ? mb91f526 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 191 confidential ? mb91f526 d a t a s h e e t 192 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential ? ordering informati on mb91f52xxxb *1 part number sub clock csv initial value lvd initial value package * 2 mb91f526lw b pmc yes on on lqfp ? 176 pin, p lastic (fpt - 1 76p - m07) mb91f526l yb pmc off mb91f526l jb pmc off on mb91f526l lb pmc off mb91f525lw b pmc o n on mb91f525l yb pmc off mb91f525l jb pmc off on mb91f525l lb pmc off mb91f524lw b pmc on on mb91f524l ybpmc off mb91f524l jbpmc off on mb91f524l lbpmc off mb91f523lw bpmc on on mb91f523l ybpmc off mb91f523l jbpmc off on mb91f523l lb pmc off mb91f522lw bpmc on on mb91f522l ybpmc off mb91f522l jbpmc off on mb91f522l lbpmc off mb91f526ls bpmc none on on mb91f526l ubpmc off mb91f526l hbpmc off on mb91f526l kbpmc off mb91f525ls bpmc on on mb91f525l ubpmc off mb9 1f525l hbpmc off on mb91f525l kbpmc off mb91f524ls bpmc on on mb91f524l ubpmc off mb91f524l hbpmc off on mb91f524l kbpmc off mb91f523ls bpmc on on mb91f523l ubpmc off mb91f523l hbpmc off on mb91f523l k bpmc off mb91f522ls bpmc on on mb91f522l ubpmc off mb91f522l hbpmc off on mb91f522l kbpmc off d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 193 c on fidential part number sub clock csv initial value lvd initial value package * 2 mb91f526kw bpmc yes on on lqfp ? 144 pin, ( lead pitch 0.5mm) p lastic (fpt - 144p - m08) mb91f526k ybpmc off mb91f526k jbpmc off on mb91f526k lbpmc off mb91f525kw bpmc on on mb91f525k ybpmc off mb91f525k jbpmc off on mb91f525k lbpmc off mb91f524kw bpmc on on mb91f524 k ybpmc off mb91f524k jbpmc off on mb91f524k lbpmc off mb91f523kw bpmc on on mb91f523k ybpmc off mb91f523k jbpmc off on mb91f523k lbpmc off mb91f522kw bpmc on on mb91f522k ybpmc off mb91f522k jbpmc off on mb91f522k lbpmc off mb9 1f526ks bpmc none on on mb91f526k u bpmc off mb91f526k h bpmc off on mb91f526k k bpmc off mb91f525ks bpmc on on mb91f525k u bpmc off mb91f525k h bpmc off on mb91f525k k bpmc off mb91f524ks bpmc on on mb91f524k u bpmc off mb91f524k h bpmc of f on mb91f524k k bpmc off mb91f523ks bpmc on on mb91f523k u bpmc off mb91f523k h bpmc off on mb91f523k k bpmc off mb91f522ks bpmc on on mb91f522k u bpmc off mb91f522k h bpmc off on mb91f522k k bpmc off d a t a s h e e t 194 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential part number sub clock csv initial value lvd initial value package * 2 mb91f526kw bpmc 1 ye s on on lqfp ? 144 pin, ( lead pitch 0.4mm) p lastic (fpt - 144p - m 12 ) mb91f526k ybpmc 1 off mb91f526k jbpmc 1 off on mb91f526k lbpmc 1 off mb91f525kw bpmc 1 on on mb91f525k ybpmc 1 off mb91f525k jbpmc 1 off on mb91f525k lbpmc 1 off mb91f524kw bpmc 1 on on mb91f524k ybpmc 1 off mb91f524k jbpmc 1 off on mb91f524k lbpmc 1 off mb91f523kw bpmc 1 on on mb91f523k ybpmc 1 off mb91f523k jbpmc 1 off on mb91f523k lbpmc 1 off mb91f522kw bpmc 1 on on mb91f522k ybpmc 1 off mb91f522k jbpmc 1 off on mb91f522 k lbpmc 1 off mb91f526ks bpmc 1 none on on mb91f526k u bpmc 1 off mb91f526k h bpmc 1 off on mb91f526k k bpmc 1 off mb91f525ks bpmc 1 on on mb91f525k u bpmc 1 off mb91f525k h bpmc 1 off on mb91f525k k bpmc 1 off mb91f524ks bpmc 1 on on mb91f524k u bpm c 1 off mb91f524k h bpmc 1 off on mb91f524k k bpmc 1 off mb91f523ks bpmc 1 on on mb91f523k u bpmc 1 off mb91f523k h bpmc 1 off on mb91f523k k bpmc 1 off mb91f522ks bpmc 1 on on mb91f522k u bpmc 1 off mb91f522k h bpmc 1 off on mb91f522k k bpmc 1 off d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 195 c on fidential part number sub clock csv initial value lvd initial value package * 2 mb91f526jw bpmc yes on on lqfp ? 120 pin, p lastic (fpt - 1 20 p - m 21 ) mb91f526j ybpmc off mb91f526j jbpmc off on mb91f526j lbpmc off mb91f525jw bpmc on on mb91f525j ybpmc off mb91f525j jbpmc off on mb91f525j lbpmc off mb91f524jw bpmc on on mb91f524j ybpmc off mb91 f524j jbpmc off on mb91f524j lbpmc off mb91f523jw bpmc on on mb91f523j ybpmc off mb91f523j jbpmc off on mb91f523j lbpmc off mb91f522jw bpmc on on mb91f522j ybpmc off mb91f522j jbpmc off on mb91f522j lbpmc off mb91f526js bpmc none on on mb91f526j ubpmc off mb91f526j hbpmc off on mb91f526j kbpmc off mb91f525js bpmc on on mb91f525j ubpmc off mb91f525j hbpmc off on mb91f525j kbpmc off mb91f524js bpmc on on mb91f524j ubpmc off mb91f524j hbpmc off on mb91f524j kbp mc off mb91f523js bpmc on on mb91f523j ubpmc off mb91f523j hbpmc off on mb91f523j kbpmc off mb91f522js bpmc on on mb91f522j ubpmc off mb91f522j hbpmc off on mb91f522j kbpmc off d a t a s h e e t 196 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential part number sub clock csv initial value lvd initial value package * 2 mb91f526fw bpmc yes on on lqfp ? 100 pin , p lastic (fpt - 1 00 p - m 20 ) mb91f526f ybpmc off mb91f526f jbpmc off on mb91f526f lbpmc off mb91f525fw bpmc on on mb91f525f ybpmc off mb91f525f jbpmc off on mb91f525f lbpmc off mb91f524fw bpmc on on mb91f524f ybpmc off mb91f524f jbpmc off on mb91f524f lbpmc off mb91f523fw bpmc on on mb91f523f ybpmc off mb91f523f jbpmc off on mb91f523f lbpmc off mb91f522fw bpmc on on mb91f522f ybpmc off mb91f522f jbpmc off on mb91f522f lbpmc off mb91f526fs bpmc none on on mb91f5 26f ubpmc off mb91f526f hbpmc off on mb91f526f kbpmc off mb91f525fs bpmc on on mb91f525f ubpmc off mb91f525f hbpmc off on mb91f525f kbpmc off mb91f524fs bpmc on on mb91f524f ubpmc off mb91f524f hbpmc off on mb91f524f kbpmc off m b91f523fs bpmc on on mb91f523f ubpmc off mb91f523f hbpmc off on mb91f523f kbpmc off mb91f522fs bpmc on on mb91f522f ubpmc off mb91f522f hbpmc off on mb91f522f kbpmc off d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 197 c on fidential part number sub clock csv initial value lvd initial value package * 2 MB91F526Dw bpmc yes on on lqfp ? 80 pin, p lastic (f pt - 80 p - m 21 ) MB91F526D ybpmc off MB91F526D jbpmc off on MB91F526D lbpmc off mb91f525dw bpmc on on mb91f525d ybpmc off mb91f525d jbpmc off on mb91f525d lbpmc off mb91f524dw bpmc on on mb91f524d ybpmc off mb91f524d jbpmc off on mb91f 524d lbpmc off mb91f523dw bpmc on on mb91f523d ybpmc off mb91f523d jbpmc off on mb91f523d lbpmc off mb91f522dw bpmc on on mb91f522d ybpmc off mb91f522d jbpmc off on mb91f522d lbpmc off MB91F526Ds bpmc none on on MB91F526D ubpmc off MB91F526D hbpmc off on MB91F526D kbpmc off mb91f525ds bpmc on on mb91f525d ubpmc off mb91f525d hbpmc off on mb91f525d kbpmc off mb91f524ds bpmc on on mb91f524d ubpmc off mb91f524d hbpmc off on mb91f524d kbpmc off mb91f523ds bpmc on on mb91f523d ubpmc off mb91f523d hbpmc off on mb91f523d kbpmc off mb91f522ds bpmc on on mb91f522d ubpmc off mb91f522d hbpmc off on mb91f522d kbpmc off d a t a s h e e t 198 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential part number sub clock csv initial value lvd initial value package * 2 mb91f526bw b pmc1 yes on on lqfp ? 64 pin, p lastic (fpt - 64 p - m 24 ) mb91f526b yb pmc1 off mb91f526b jb pmc1 off on mb91f526b lb pmc1 off mb91f525bw b pmc1 on on mb91f525b yb pmc1 off mb91f525b jb pmc1 off on mb91f525b lb pmc1 off mb91f524bw b pmc1 on on mb91f524b yb pmc1 off mb91f524b jb pmc1 off on mb91f524b lb pmc1 off mb91f523bw b pmc1 on on mb91f523b yb pmc1 off mb91f523b jb pmc1 off on mb91f523b lb pmc1 off mb91f522bw b pmc1 on on mb91f522b yb pmc1 off mb91f522b jb pmc1 off on mb91f522b lb pmc1 off mb91f 526bs b pmc1 none on on mb91f526b u b pmc1 off mb91f526b h b pmc1 off on mb91f526b k b pmc1 off mb91f525bs b pmc1 on on mb91f525b u b pmc1 off mb91f525b h b pmc1 off on mb91f525b k b pmc1 off mb91f524bs b pmc1 on on mb91f524b u b pmc1 off mb91f524b h b pmc1 off on mb91f524b k b pmc1 off mb91f523bs b pmc1 on on mb91f523b u b pmc1 off mb91f523b h b pmc1 off on mb91f523b k b pmc1 off mb91f522bs b pmc1 on on mb91f522b u b pmc1 off mb91f522b hb pmc1 off on mb91f522b k b pmc1 off * 1 : it is on ly sup ported for customers who have already adopted it now . we d o n ot recommend adopting new products . * 2 : for details of the package , see " ? package dimensi on s ". d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 199 c on fidential ? ordering informati on mb91f52xxxc part number sub clock csv initial value lvd initial value package * mb91f526lw cpmc yes on on lqfp ? 176 pin, p lastic (fpt - 1 76p - m07) mb91f526l ycpmc off mb91f526l jcpmc off on mb91f526l lcpmc o ff mb91f525lw cpmc on on mb91f525l ycpmc off mb91f525l jcpmc off on mb91f525l lcpmc off mb91f524lw cpmc on on mb91f524l ycpmc off mb91f524l jcpmc off on mb91f524l lcpmc off mb91f523lw cpmc on on mb91f523l ycpmc off mb91f523l jcpmc off on mb91f523l lcpmc off mb91f522lw cpmc on on mb91f522l ycpmc off mb91f522l jcpmc off on mb91f522l lcpmc off mb91f526ls cpmc none on on mb91f526l ucpmc off mb91f526l hcpmc off on mb91f526l kcpmc off mb91f525ls cpmc on on mb91 f525l ucpmc off mb91f525l hcpmc off on mb91f525l kcpmc off mb91f524ls cpmc on on mb91f524l ucpmc off mb91f524l hcpmc off on mb91f524l kcpmc off mb91f523ls cpmc on on mb91f523l ucpmc off mb91f523l hcpmc off on mb91f523l kcpmc off mb91f522ls cpmc on on mb91f522l ucpmc off mb91f522l hcpmc off on mb91f522l kcpmc off d a t a s h e e t 200 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential part number sub clock csv initial value lvd initial value package * mb91f526kw cpmc yes on on lqfp ? 144 pin, ( lead pitch 0.5mm) p lastic (fpt - 144p - m08) mb91f526k ycpmc off mb91f526k jcpmc off on mb91f526k lcpmc off mb91f525kw cpmc on on mb91f525k ycpmc off mb91f525k jcpmc off on mb91f525k lcpmc off mb91f524kw cpmc on on mb91f524 k ycpmc off mb91f524k jcpmc off on mb91f524k lcpmc off mb91f523kw cpmc on on mb91f523k ycpmc off mb91f523k jcpmc off on mb91f523k lcpmc off mb91f522kw cpmc on on mb91f522k ycpmc off mb91f522k jcpmc off on mb91f522k lcpmc off mb9 1f526ks cpmc none on on mb91f526k ucpmc off mb91f526k hcpmc off on mb91f526k kcpmc off mb91f525ks cpmc on on mb91f525k ucpmc off mb91f525k hcpmc off on mb91f525k kcpmc off mb91f524ks cpmc on on mb91f524k ucpmc off mb91f524k hcpmc of f on mb91f524k kcpmc off mb91f523ks cpmc on on mb91f523k ucpmc off mb91f523k hcpmc off on mb91f523k kcpmc off mb91f522ks cpmc on on mb91f522k ucpmc off mb91f522k hcpmc off on mb91f522k kcpmc off d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 201 c on fidential part number sub clock csv initial value lvd initial value package * mb91f526kw cpmc 1 ye s on on lqfp ? 144 pin, ( lead pitch 0.4mm) p lastic (fpt - 144p - m 12 ) mb91f526k ycpmc 1 off mb91f526k jcpmc 1 off on mb91f526k lcpmc 1 off mb91f525kw cpmc 1 on on mb91f525k ycpmc 1 off mb91f525k jcpmc 1 off on mb91f525k lcpmc 1 off mb91f524kw cpmc 1 on on mb91f524k ycpmc 1 off mb91f524k jcpmc 1 off on mb91f524k lcpmc 1 off mb91f523kw cpmc 1 on on mb91f523k ycpmc 1 off mb91f523k jcpmc 1 off on mb91f523k lcpmc 1 off mb91f522kw cpmc 1 on on mb91f522k ycpmc 1 off mb91f522k jcpmc 1 off on mb91f522 k lcpmc 1 off mb91f526ks cpmc 1 none on on mb91f526k ucpmc 1 off mb91f526k hcpmc 1 off on mb91f526k kcpmc 1 off mb91f525ks cpmc 1 on on mb91f525k ucpmc 1 off mb91f525k hcpmc 1 off on mb91f525k kcpmc 1 off mb91f524ks cpmc 1 on on mb91f524k ucpm c 1 off mb91f524k hcpmc 1 off on mb91f524k kcpmc 1 off mb91f523ks cpmc 1 on on mb91f523k ucpmc 1 off mb91f523k hcpmc 1 off on mb91f523k kcpmc 1 off mb91f522ks cpmc 1 on on mb91f522k ucpmc 1 off mb91f522k hcpmc 1 off on mb91f522k kcpmc 1 off d a t a s h e e t 202 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential part number sub clock csv initial value lvd initial value package * mb91f526jw cpmc yes on on lqfp ? 120 pin, p lastic (fpt - 1 20 p - m 21 ) mb91f526j ycpmc off mb91f526j jcpmc off on mb91f526j lcpmc off mb91f525jw cpmc on on mb91f525j ycpmc off mb91f525j jcpmc off on mb91f525j lcpmc off mb91f524jw cpmc on on mb91f524j ycpmc off mb91 f524j jcpmc off on mb91f524j lcpmc off mb91f523jw cpmc on on mb91f523j ycpmc off mb91f523j jcpmc off on mb91f523j lcpmc off mb91f522jw cpmc on on mb91f522j ycpmc off mb91f522j jcpmc off on mb91f522j lcpmc off mb91f526js cpmc none on on mb91f526j ucpmc off mb91f526j hcpmc off on mb91f526j kcpmc off mb91f525js cpmc on on mb91f525j ucpmc off mb91f525j hcpmc off on mb91f525j kcpmc off mb91f524js cpmc on on mb91f524j ucpmc off mb91f524j hcpmc off on mb91f524j kcp mc off mb91f523js cpmc on on mb91f523j ucpmc off mb91f523j hcpmc off on mb91f523j kcpmc off mb91f522js cpmc on on mb91f522j ucpmc off mb91f522j hcpmc off on mb91f522j kcpmc off d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 203 c on fidential part number sub clock csv initial value lvd initial value package * mb91f526fw cpmc yes on on lqfp ? 100 pin , p lastic (fpt - 1 00 p - m 20 ) mb91f526f ycpmc off mb91f526f jcpmc off on mb91f526f lcpmc off mb91f525fw cpmc on on mb91f525f ycpmc off mb91f525f jcpmc off on mb91f525f lcpmc off mb91f524fw cpmc on on mb91f524f ycpmc off mb91f524f jcpmc off on mb91f524f lcpmc off mb91f523fw cpmc on on mb91f523f ycpmc off mb91f523f jcpmc off on mb91f523f lcpmc off mb91f522fw cpmc on on mb91f522f ycpmc off mb91f522f jcpmc off on mb91f522f lcpmc off mb91f526fs cpmc none on on mb91f5 26f ucpmc off mb91f526f hcpmc off on mb91f526f kcpmc off mb91f525fs cpmc on on mb91f525f ucpmc off mb91f525f hcpmc off on mb91f525f kcpmc off mb91f524fs cpmc on on mb91f524f ucpmc off mb91f524f hcpmc off on mb91f524f kcpmc off m b91f523fs cpmc on on mb91f523f ucpmc off mb91f523f hcpmc off on mb91f523f kcpmc off mb91f522fs cpmc on on mb91f522f ucpmc off mb91f522f hcpmc off on mb91f522f kcpmc off d a t a s h e e t 204 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 c on fidential part number sub clock csv initial value lvd initial value package * MB91F526Dw cpmc yes on on lqfp ? 80 pin, p lastic (f pt - 80 p - m 21 ) MB91F526D ycpmc off MB91F526D jcpmc off on MB91F526D lcpmc off mb91f525dw cpmc on on mb91f525d ycpmc off mb91f525d jcpmc off on mb91f525d lcpmc off mb91f524dw cpmc on on mb91f524d ycpmc off mb91f524d jcpmc off on mb91f 524d lcpmc off mb91f523dw cpmc on on mb91f523d ycpmc off mb91f523d jcpmc off on mb91f523d lcpmc off mb91f522dw cpmc on on mb91f522d ycpmc off mb91f522d jcpmc off on mb91f522d lcpmc off MB91F526Ds cpmc none on on MB91F526D ucpmc off MB91F526D hcpmc off on MB91F526D kcpmc off mb91f525ds cpmc on on mb91f525d ucpmc off mb91f525d hcpmc off on mb91f525d kcpmc off mb91f524ds cpmc on on mb91f524d ucpmc off mb91f524d hcpmc off on mb91f524d kcpmc off mb91f523ds cpmc on on mb91f523d ucpmc off mb91f523d hcpmc off on mb91f523d kcpmc off mb91f522ds cpmc on on mb91f522d ucpmc off mb91f522d hcpmc off on mb91f522d kcpmc off d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 205 c on fidential part number sub clock csv initial value lvd initial value package * mb91f526bw cpmc1 yes on on lqfp ? 64 pin, p lastic (fpt - 64 p - m 24 ) mb91f526b ycpmc1 off mb91f526b jcpmc1 off on mb91f526b lcpmc1 off mb91f525bw cpmc1 on on mb91f525b ycpmc1 off mb91f525b jcpmc1 off on mb91f525b lcpmc1 off mb91f524bw cpmc1 on on mb91f524b ycpmc1 off mb91f524b jcpmc1 off on mb91f524b lcpmc1 off mb91f523bw cpmc1 on on mb91f523b ycpmc1 off mb91f523b jcpmc1 off on mb91f523b lcpmc1 off mb91f522bw cpmc1 on on mb91f522b ycpmc1 off mb91f522b jcpmc1 off on mb91f522b lcpmc1 off mb91f 526bs cpmc1 none on on mb91f526b ucpmc1 off mb91f526b hcpmc1 off on mb91f526b kcpmc1 off mb91f525bs cpmc1 on on mb91f525b ucpmc1 off mb91f525b hcpmc1 off on mb91f525b kcpmc1 off mb91f524bs cpmc1 on on mb91f524b ucpmc1 off mb91f524b hcpmc1 off on mb91f524b kcpmc1 off mb91f523bs cpmc1 on on mb91f523b ucpmc1 off mb91f523b hcpmc1 off on mb91f523b kcpmc1 off mb91f522bs cpmc1 on on mb91f522b ucpmc1 off mb91f522b hcpmc1 off on mb91f522b kcpmc1 off *: for deta ils of the package , see " ? package dimensi on s ". datasheet ? package dimensions 64-pin plastic lqfp lead pitch 0.50 m m package width package length 10.0 10.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.32 g code (reference ) p-lfqfp64-1 0 10-0.50 64-pin plastic lqf p (fpt-64p-m24) (fpt -64p-m24) lead no. details of "a" part 0.25(.010) (stand off) 0.100.10 0.600.15 (.024.006) 0.500.20 (.020.008) 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ~8 "a" 0.08(.003) 0.1450.055 (.006.002) 0.08(.003) m (.008.002) 0.200.05 0.50(.020) 12.000.20(.472.008)sq index 49 64 33 48 17 32 16 1 2005-2010 fujitsu semiconductor limited f64036s-c-1-3 c (mounting height) *10.000.10(.394.004)sq dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. (.004.004) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ 206 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential datasheet 80-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 12 mm 12 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.47 g code (reference ) p-lfqfp80-1 2 12-0.50 80-pin plastic lqfp (fpt-80p-m21) (fpt-80p-m21) c 2006-2010 fujitsu semiconductor limited f80035s-c-2-4 1 20 40 21 60 41 80 61 index 12.000.10(.472.004)sq 14.000.20(.551.008)sq 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.006.002) 0.08(.003) "a" 0~8 .059 ?.004 +.008 ?0.10 +0.20 1.50 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.05 (.004.002) (stand off) 0.25(.010) details of "a" part lead no. (mounting height) * dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 207 confidential datasheet 100-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 14.0 mm 14.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.65 g code (reference ) p-lfqfp100-14 14-0.5 0 100-pin plastic lqfp (fpt -100p-m20) (fpt-100p-m20) c 2005 -2010 fujitsu semiconductor limited f100031s-c-3-5 16.00 0.20(.630 .008)sq 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.008 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" index .059 ? .004 +.008 ? 0.10 +0.20 1.50 (mounting height) 0 ~8 0.50 0.20 (.020 .008 ) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) details of "a" part (stand off) * 14.00 0.10(.551 .004)sq dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. p lease confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ 208 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential datasheet 120-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 16.0 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.88 g code (reference ) p-lfqfp120-16 16-0.5 0 120-pin plastic lqfp (fpt -120p-m21) (fpt-120p-m21) c 2002-2010 fujitsu semiconductor limited f120033s-c-4-7 1 30 60 31 90 61 120 91 sq 18.000.20(.709.008)sq 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) index .006 ?.001 +.002 ?0.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?.004 +.008 ?0.10 +0.20 1.50 details of "a" part (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0~8 * .630 ?.004 +.016 ?0.10 +0.40 16.00 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. resin protrusion is +0.25(.010) max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 209 confidential datasheet 144-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 20.0 20.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 1.20 g code (reference ) p-lfqfp144-20 20-0.5 0 144-pin plastic lqfp (fpt -144p-m08) (fpt-144p-m08) c 2003-2010 fujitsu semiconductor limited f144019s-c-4-8 details of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ~8 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 22.000.20(.866.008)sq (mounting height) * 20.000.10(.787.004)sq dimensions in mm (inches). note: the values in parentheses are reference values. note 1) *:values do not include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest p ackage dimension by following url. http://edevice.fujitsu.com/package/ en - search/ 210 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential datasheet 144-pin plastic lqfp lead pitch 0.40 mm pa ck age width pa ck age length 16.0 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max we ight 0.88 g code (reference ) p-lfqfp144-16 16-0.4 0 144-pin plastic lqfp (fpt -144p-m12) (fpt-144p-m12) c 2003-2010 fujitsu semiconductor limited f144024s-c-3-5 .059 ? .004 +.008 ? 0.10 +0.20 1.50 details of "a" part 0~8 (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0.08(.003) 0.145 ? 0.03 +.002 ? .001 .006 +0.05 "a" .007.001 0.180.035 m 0.07(.003) 36 37 1 lead no. 0.40(.016) index 144 109 108 18.000.20(.709.008)sq sq 16.00 73 72 * .630 ? .004 +.016 ? 0.10 +0.40 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 211 confidential datasheet 176-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 24.0 24.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x code (reference ) p-lqfp-0176-2424-0.5 0 176-pin plastic lqfp (fpt -176p-m07) (fpt-176p-m07) c details of "a" part 0~8 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) (stand off) (.004.004) 0.100.10 1.50 +0.20 ?0.10 +.008 ?.004 .059 (mounting height) 0.08(.003) (.006.002) 0.1450.055 "a" index 1 lead no. 44 45 88 89 132 133 176 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) *24.000.10(.945.004)sq 26.000.20(1.024.008)sq dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : values do not include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness note 3) pins width do not include tie bar cutting remainder. 2004-2010 fujitsu semiconductor limited f176013s-c-1-3 please confirm the latest package dimension by foll owing url. http://edevice.fujitsu.com/package/ en - search/ 212 mb91f526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 213 confidential major changes page section change results revision 1.0 - - initial release revision 2.0 3 features corrected the following description. 5v tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 automotive input 5v tolerant input: 4 channel s ch.6, ch.8, ch.9, ch.11 cmos hysteresis input 33 to 36 i/o circuit type corrected the following description to " type f, g, i, j, k , m " . schmitt input cmos hysteresis input corrected the following description to " type d, e " . i 2 c schmitt input i 2 c h ysteresis input 44 to 49 block diagram corrected the following description. mb91f522b, mb91f523b, mb91f524b, mb91f525b, mb91f526b mb91f522d, mb91f523d, mb91f524d, mb91f525d, MB91F526D mb91f522f, mb91f523f, mb91f524f, mb91f525f, mb91f526f mb91f522j, m b91f523j, mb91f524j, mb91f525j, mb91f526j mb91f522k, mb91f523k, mb91f524k, mb91f525k, mb91f526k mb91f522l, mb91f523l, mb91f524l, mb91f525l, mb91f526l 138 electrical characteristics 2. recommended operating conditions added the following description. *1 when it is used outside recommended operation guarantee range (range of the operation guarantee),contact your sales representative. moreover, minimum value with an effective external low - vol tage detection reset becomes a voltage until generating low - volta ge detection reset 139,140 electrical characteristics 3.dc characteristics corrected the value of "icct5 when using sub clock 32khz ta=+25 c ". max 1420 a max 2000 a 139 electrical characteristics 3.dc characteristics corrected the value of "power su pply voltage range". ( ta: - 40 c to +105 c ,vcc=avcc=2.7v to 5.5v,vss=avss=0.0v) (t a : - 40 c to +105 c ,vcc=avcc=5.0v 10%/3.3v 0.3v ,v ss =av ss =0.0v) 140,141 electrical characteristics 3.dc characteristics corrected the value of "power supply volta ge range". ( t a : - 40c to +125 c ,vcc=avcc=2.7v to 5.5v,vss=avss=0.0v) (t a : - 40 c to +125 c ,vcc=avcc=5.0v 10%/3.3v 0.3v ,v ss =av ss =0.0v) 141 electrical characteristics 3.dc characteristics corrected the value of " pull - up resistance r up1 ". vcc=3.3v0.3v min 49 max 140 min 45 max 140 141 electrical characteristics 3.dc characteristics corrected the following description. pull - up resistance r up2 port pin other than p035,041,093,122 p073,074,076,077 141 electrical characteristics 3.dc characteristics corrected the value of " pull - up resistance r up2 ". vcc=5.0v10% min 25 max 100 min 25 max 60 vcc=3.3v0.3v min 49 max 140 min 33 max 90 141 electrical characteristics 3.dc characteristics added the value of " pull - up resistance r u p 3 ". pin name : port pin other than p035,041,073,074,076,077,093,122 vcc=5.0v10% min 25 max 100 vcc=3.3v0.3v min 45 max 140 150,152, 154,156 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 1),(4 - 1 - 2),( 4 - 1 - 3),(4 - 1 - 4) (4 - 1 - 1),(4 - 1 - 4)sck ? sot delay time t slovi (4 - 1 - 2),(4 - 1 - 3)sck ? sot delay time t shovi corrected the following description. pin name: sck0 to sck11 sot0 to sot11 value: min - 30 max 30 pin name: sck0 to sck2 , sck5 to sck11 sot0 to sot2 , sot5 t o sot11 value: min - 30 max 30 pin name: sck3,sck4 s ot 3,s ot 4 value: min - 300 max 300 d a t a s h e e t 214 mb91f 526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential page section change results 150,152, 154,156 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 1),(4 - 1 - 2),(4 - 1 - 3),(4 - 1 - 4) (4 - 1 - 1),(4 - 1 - 4 ) valid sin ? sck setup time t ivshi (4 - 1 - 2),(4 - 1 - 3 ) valid sin ? sck setup time t ivsli corrected the following description. pin name: sck0 to sck11 sin0 to sin11 value: min 34 max - pin name: sck0 to sck2 , sck5 to sck11 sin0 to sin2 , sin5 to sin11 value: min 34 max - pi n name: sck3,sck4 , sin3,sin4 value: min 300 max - 150,152, 154,156 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 1),(4 - 1 - 2),(4 - 1 - 3),(4 - 1 - 4) (4 - 1 - 1),(4 - 1 - 4 ) sck ? sot delay time t slove (4 - 1 - 2),(4 - 1 - 3 ) sck ? sot delay time t shove corrected the following description. pin name: sck0 to sck11 sot0 to sot11 value: min - max 33 pin name: sck0 to sck2,sck5 to sck11 sot0 to sot2,sot5 to sot11 value: min - max 33 pin name: sck3,sck4 s ot 3,s ot 4 value: min - max 3 00 150,152, 154,156 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 1),(4 - 1 - 2),(4 - 1 - 3),(4 - 1 - 4) (4 - 1 - 1),(4 - 1 - 2),(4 - 1 - 3),(4 - 1 - 4) sck fall time t f corrected the following description. pin name: sck0 to sck2,s ck5 to sck11 value: min - max 5 pin name: sck3,sck4 value: min - max 250 pin name: sck0 to sck 11 value: min - max 5 158,161, 164,167 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 5),(4 - 1 - 6),(4 - 1 - 7),(4 - 1 - 8) (4 - 1 - 5)scs ? sck setup time t cssi (4 - 1 - 6)scs ? sck setup time t cssi (4 - 1 - 7)scs ? sck setup time t cssi (4 - 1 - 8)scs ? sck setup time t cssi corrected the following description. pin name: sck1 to sck11 scs1 to scs3,scs40 to scs43,scs50 to scs53,scs60 to scs63,scs70 to scs73,scs8 to scs11 value: min t cssu +0 max t cssu +50 pin name: sck1,sck2,sck5 to sck11 scs1,scs2,scs50 to scs53,scs60 to scs63,scs70 to scs73,scs8 to scs11 value: min t cssu - 50 max t cssu +0 pin name: sck3,sck4 scs3,scs40 to scs43 value : min t cssu - 50 max t cssu +300 158,161, 164,167 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 5),(4 - 1 - 6),(4 - 1 - 7),(4 - 1 - 8) (4 - 1 - 5)sck ? scs hold time t cshi (4 - 1 - 6 )sck ? scs hold time t cshi (4 - 1 - 7 )sck ? scs hol d time t cshi (4 - 1 - 8 )sck ? scs hold time t cshi corrected the following description. pin name: sck1 to sck11 scs1 to scs3,scs40 to scs43,scs50 to scs53,scs60 to scs63,scs70 to scs73,scs8 to scs11 value: min t cshd - 50 max t cshd +0 pin name: sck1,sck2,sck5 to sck11 scs1,scs2,scs50 to scs53,scs60 to scs63,scs70 to scs73,scs8 to scs11 value: min t cshd - 10 max t cshd +50 pin name: sck3,sck4 scs3,scs40 to scs43 value: min t cshd - 300 max t cshd +50 d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 215 confidential page section change results 158,161, 164,167 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 5),(4 - 1 - 6),(4 - 1 - 7),(4 - 1 - 8) (4 - 1 - 5) , (4 - 1 - 6 )scs ? sot delay time t dse (4 - 1 - 7 ) , (4 - 1 - 8 ) scs ? sot delay time t dse corrected the following description. pin name: scs1 to scs3,scs40 to scs43,scs50 to scs53,scs60 to scs63 ,scs70 to scs73,scs8 to scs11 sot1 to sot11 value: min - max 40 pin name: scs1,scs2 , scs50 to scs53 , scs60 to scs63 , scs70 to scs73 , scs8 to scs11 sot1,sot2,sot5 to sot11 value: min - max 40 pin name: scs3,scs40 to scs43 sot3,sot4 value: min - max 300 15 9,162, 165,168 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 5),(4 - 1 - 6),(4 - 1 - 7),(4 - 1 - 8) (4 - 1 - 5)sck ? scs clock switch time t scc (4 - 1 - 6 )sck ? scs clock switch time t scc (4 - 1 - 7 )sck ? scs clock switch time t scc (4 - 1 - 8 )sck ? scs clock switch time t scc corrected the following description. pin name: sck1 to sck11 scs1 to scs3,scs40 to scs43,scs50 to scs53,scs60 to scs63,scs70 to scs73,scs8 to scs11 value: min 3t cpp +0 max 3t cpp +50 pin name: sck1,sck2,sck5 to sck11 scs1,scs2,scs50 to scs53,scs60 to scs63,scs70 to scs73,scs8 to scs11 value: min 3t cpp - 10 max 3t cpp +50 pin name: sck3,sck4 scs3,scs40 to scs43 value: min 3t cpp - 300 max 3t cpp +50 159,162, 165,168 electrical characteristics 4. ac characteristics (4) multi - function serial (4 - 1) csio timing (4 - 1 - 5),(4 - 1 - 6),(4 - 1 - 7),(4 - 1 - 8) added the following description. regardless of the deselect time setting, once after the serial chip select pin becomes inac tive, it will take at least five peripheral bus clock cycles to be active again 184 electrical characteristics 5.a/d converter (1) 12 - bit a/d converter electrical characteristics added the value of " total error ". total error value min C typ C max 12 lsb 184 electrical characteristics 5.a/d converter (1) 12 - bi t a/d converter electrical characteristics corrected the value of " zero transition voltage ". min avrl+0.5lsb - 20mv max avrl+0.5lsb+20mv min avrl - 11.5lsb max avrl+12.5lsb 184 electrical characteristics 5.a/d converter (1) 12 - bit a/d converter electr ical characteristics corrected the value of "full - scale transition voltage". min avrh - 1.5lsb - 20mv max avrh - 1.5lsb+20mv min avrh - 13.5lsb max avrh+10.5lsb 184 electrical characteristics 5.a/d converter (1) 12 - bit a/d converter electrical characteris tics added the following description. parameter : power supply current i a avcc*3 *3: the power supply current described only current value on a/d converter. the total avcc current value must be calculated the power supply current for a/d converter and d/a converter. 188 electrical characteristics 7.d/a converter added the following description. parameter : power supply current *1 *1: the power supply current described only current value on d/a converter.the total avcc current value must be calculated th e power su pply current for d/a converter and a/d converter. 187 electrical characteristics 6.flash memory parameter: erase cycle*2/ data retain time deleted the following description. remarks : " temperature at writing/erasing tj < +105 c " d a t a s h e e t 216 mb91f 526l_ds705 - 00011 - 2 v 0 - e, january 31, 2014 confidential page section change results 188 electrical c haracteristics 7.d/a converter corrected the following description. parameter : power supply current symbol ia pin name av cc symbol iah pin name av cc symbol ia pin name avcc symbol iah pin name avcc 190 example characteristics corrected the followin g description. watch mode 192 ordering information corrected the following description. ordering information ordering information mb91f52xxxb *1 package package* 2 198 ordering information added the following description. * 1 : it is only suppo rted for customers who have already adopted it now . we do not recommend adopting new products . 198 ordering information corrected the following description. for details of the package, see " package dimensions ". * 2 : for details of the package, se e " package dimensions ". 199 to 20 5 ordering information added the following description. ordering information mb91f52xxxc - - company name and layout design change d a t a s h e e t january 31, 2014 , mb91f526l_ds705 - 00011 - 2 v 0 - e 217 confidential d a t a s h e e t 218 mb91f526l_ds705-00011-2v0- e, january 31, 2014 confidential colophon the products described in this document are designed, developed and manufactured as co ntemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injur y, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, ai r traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion wil l not be liable to you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. if any products described in this document represent good s or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective governmen t entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantabili ty, non - infringement of third - party rights, or any other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2013 - 2014 spansion inc. al l rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. |
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